cp1emu.c (a8ff66f52d3f17b5ae793955270675c197f73d6c) cp1emu.c (f1b44067c19258b7614e3cd09dfe8d8e12ff5895)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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584 *contpc = regs->cp0_epc +
585 dec_insn.pc_inc +
586 dec_insn.next_pc_inc;
587 return 1;
588 case bgtzl_op:
589 if (NO_R6EMU)
590 break;
591 case bgtz_op:
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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584 *contpc = regs->cp0_epc +
585 dec_insn.pc_inc +
586 dec_insn.next_pc_inc;
587 return 1;
588 case bgtzl_op:
589 if (NO_R6EMU)
590 break;
591 case bgtz_op:
592 /*
593 * Compact branches for R6 for the
594 * bgtz and bgtzl opcodes.
595 * BGTZ | rs = 0 | rt != 0 == BGTZALC
596 * BGTZ | rs = rt != 0 == BLTZALC
597 * BGTZ | rs != 0 | rt != 0 == BLTUC
598 * BGTZL | rs = 0 | rt != 0 == BGTZC
599 * BGTZL | rs = rt != 0 == BLTZC
600 * BGTZL | rs != 0 | rt != 0 == BLTC
601 *
602 * *ZALC varint for BGTZ &&& rt != 0
603 * For real GTZ{,L}, rt is always 0.
604 */
605 if (cpu_has_mips_r6 && insn.i_format.rt) {
606 if ((insn.i_format.opcode == blez_op) &&
607 ((!insn.i_format.rs && insn.i_format.rt) ||
608 (insn.i_format.rs == insn.i_format.rt)))
609 regs->regs[31] = regs->cp0_epc +
610 dec_insn.pc_inc;
611 *contpc = regs->cp0_epc + dec_insn.pc_inc +
612 dec_insn.next_pc_inc;
613
614 return 1;
615 }
616
592 if ((long)regs->regs[insn.i_format.rs] > 0)
593 *contpc = regs->cp0_epc +
594 dec_insn.pc_inc +
595 (insn.i_format.simmediate << 2);
596 else
597 *contpc = regs->cp0_epc +
598 dec_insn.pc_inc +
599 dec_insn.next_pc_inc;

--- 1434 unchanged lines hidden --- 		617 if ((long)regs->regs[insn.i_format.rs] > 0)
618 *contpc = regs->cp0_epc +
619 dec_insn.pc_inc +
620 (insn.i_format.simmediate << 2);
621 else
622 *contpc = regs->cp0_epc +
623 dec_insn.pc_inc +
624 dec_insn.next_pc_inc;

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