cp1emu.c (70e4c234aa48e11c0575364939dfab4cb27b2172) cp1emu.c (c410352699e2a1adc77969f19eb63030e610d048)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1229 scoptop:
1230 SPFROMREG(fr, MIPSInst_FR(ir));
1231 SPFROMREG(fs, MIPSInst_FS(ir));
1232 SPFROMREG(ft, MIPSInst_FT(ir));
1233 fd = (*handler) (fr, fs, ft);
1234 SPTOREG(fd, MIPSInst_FD(ir));
1235
1236 copcsr:
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1229 scoptop:
1230 SPFROMREG(fr, MIPSInst_FR(ir));
1231 SPFROMREG(fs, MIPSInst_FS(ir));
1232 SPFROMREG(ft, MIPSInst_FT(ir));
1233 fd = (*handler) (fr, fs, ft);
1234 SPTOREG(fd, MIPSInst_FD(ir));
1235
1236 copcsr:
1237 if (ieee754_cxtest(IEEE754_INEXACT))
1237 if (ieee754_cxtest(IEEE754_INEXACT)) {
1238 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1238 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1239 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1239 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1240 }
1241 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1242 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1240 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1243 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1241 if (ieee754_cxtest(IEEE754_OVERFLOW))
1244 }
1245 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1246 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1242 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1247 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1243 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1248 }
1249 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1250 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1244 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1251 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1252 }
1245
1246 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1247 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1248 /*printk ("SIGFPE: FPU csr = %08x\n",
1249 ctx->fcr31); */
1250 return SIGFPE;
1251 }
1252

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1463
1464 rv.s = (*handler.b) (fs, ft);
1465 goto copcsr;
1466scopuop:
1467 SPFROMREG(fs, MIPSInst_FS(ir));
1468 rv.s = (*handler.u) (fs);
1469 goto copcsr;
1470copcsr:
1253
1254 ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
1255 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1256 /*printk ("SIGFPE: FPU csr = %08x\n",
1257 ctx->fcr31); */
1258 return SIGFPE;
1259 }
1260

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1471
1472 rv.s = (*handler.b) (fs, ft);
1473 goto copcsr;
1474scopuop:
1475 SPFROMREG(fs, MIPSInst_FS(ir));
1476 rv.s = (*handler.u) (fs);
1477 goto copcsr;
1478copcsr:
1471 if (ieee754_cxtest(IEEE754_INEXACT))
1479 if (ieee754_cxtest(IEEE754_INEXACT)) {
1480 MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
1472 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1481 rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
1473 if (ieee754_cxtest(IEEE754_UNDERFLOW))
1482 }
1483 if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
1484 MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
1474 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1485 rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
1475 if (ieee754_cxtest(IEEE754_OVERFLOW))
1486 }
1487 if (ieee754_cxtest(IEEE754_OVERFLOW)) {
1488 MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
1476 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1489 rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
1477 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE))
1490 }
1491 if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
1492 MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
1478 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1493 rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
1479 if (ieee754_cxtest(IEEE754_INVALID_OPERATION))
1494 }
1495 if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
1496 MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
1480 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1497 rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
1498 }
1481 break;
1482
1483 /* unary conv ops */
1484 case fcvts_op:
1485 return SIGILL; /* not defined */
1486
1487 case fcvtd_op:
1488 SPFROMREG(fs, MIPSInst_FS(ir));

--- 448 unchanged lines hidden --- 		1499 break;
1500
1501 /* unary conv ops */
1502 case fcvts_op:
1503 return SIGILL; /* not defined */
1504
1505 case fcvtd_op:
1506 SPFROMREG(fs, MIPSInst_FS(ir));

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