| cp1emu.c (69b9a2fd05a308b9b1e1f282f3b772491603c582) | cp1emu.c (28d6f93d201d20ce47a9e8414655569a78f0353c) |
|---|---|
| 1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. --- 672 unchanged lines hidden (view full) --- 681 return 1; 682 case beqzcjic_op: 683 if (!cpu_has_mips_r6) 684 break; 685 *contpc = regs->cp0_epc + dec_insn.pc_inc + 686 dec_insn.next_pc_inc; 687 688 return 1; | 1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. --- 672 unchanged lines hidden (view full) --- 681 return 1; 682 case beqzcjic_op: 683 if (!cpu_has_mips_r6) 684 break; 685 *contpc = regs->cp0_epc + dec_insn.pc_inc + 686 dec_insn.next_pc_inc; 687 688 return 1; |
| 689 case bnezcjialc_op: 690 if (!cpu_has_mips_r6) 691 break; 692 if (!insn.i_format.rs) 693 regs->regs[31] = regs->cp0_epc + 4; 694 *contpc = regs->cp0_epc + dec_insn.pc_inc + 695 dec_insn.next_pc_inc; 696 697 return 1; |
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| 689#endif 690 case cop0_op: 691 case cop1_op: 692 /* Need to check for R6 bc1nez and bc1eqz branches */ 693 if (cpu_has_mips_r6 && 694 ((insn.i_format.rs == bc1eqz_op) || 695 (insn.i_format.rs == bc1nez_op))) { 696 bit = 0; --- 1400 unchanged lines hidden --- | 698#endif 699 case cop0_op: 700 case cop1_op: 701 /* Need to check for R6 bc1nez and bc1eqz branches */ 702 if (cpu_has_mips_r6 && 703 ((insn.i_format.rs == bc1eqz_op) || 704 (insn.i_format.rs == bc1nez_op))) { 705 bit = 0; --- 1400 unchanged lines hidden --- |