cp1emu.c (4e9561b20e2f5c1170704a81ec7e1ac961ba5e68) cp1emu.c (a79f5f9ba5088f157482feaa6ae2bacc9da0f5db)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1834 return SIGILL;
1835
1836 SPFROMREG(ft, MIPSInst_FT(ir));
1837 SPFROMREG(fs, MIPSInst_FS(ir));
1838 rv.s = ieee754sp_fmina(fs, ft);
1839 break;
1840 }
1841
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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1834 return SIGILL;
1835
1836 SPFROMREG(ft, MIPSInst_FT(ir));
1837 SPFROMREG(fs, MIPSInst_FS(ir));
1838 rv.s = ieee754sp_fmina(fs, ft);
1839 break;
1840 }
1841
1842 case fmax_op: {
1843 union ieee754sp fs, ft;
1844
1845 if (!cpu_has_mips_r6)
1846 return SIGILL;
1847
1848 SPFROMREG(ft, MIPSInst_FT(ir));
1849 SPFROMREG(fs, MIPSInst_FS(ir));
1850 rv.s = ieee754sp_fmax(fs, ft);
1851 break;
1852 }
1853
1854 case fmaxa_op: {
1855 union ieee754sp fs, ft;
1856
1857 if (!cpu_has_mips_r6)
1858 return SIGILL;
1859
1860 SPFROMREG(ft, MIPSInst_FT(ir));
1861 SPFROMREG(fs, MIPSInst_FS(ir));
1862 rv.s = ieee754sp_fmaxa(fs, ft);
1863 break;
1864 }
1865
1842 case fabs_op:
1843 handler.u = ieee754sp_abs;
1844 goto scopuop;
1845
1846 case fneg_op:
1847 handler.u = ieee754sp_neg;
1848 goto scopuop;
1849

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2128 return SIGILL;
2129
2130 DPFROMREG(ft, MIPSInst_FT(ir));
2131 DPFROMREG(fs, MIPSInst_FS(ir));
2132 rv.d = ieee754dp_fmina(fs, ft);
2133 break;
2134 }
2135
1866 case fabs_op:
1867 handler.u = ieee754sp_abs;
1868 goto scopuop;
1869
1870 case fneg_op:
1871 handler.u = ieee754sp_neg;
1872 goto scopuop;
1873

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2152 return SIGILL;
2153
2154 DPFROMREG(ft, MIPSInst_FT(ir));
2155 DPFROMREG(fs, MIPSInst_FS(ir));
2156 rv.d = ieee754dp_fmina(fs, ft);
2157 break;
2158 }
2159
2160 case fmax_op: {
2161 union ieee754dp fs, ft;
2162
2163 if (!cpu_has_mips_r6)
2164 return SIGILL;
2165
2166 DPFROMREG(ft, MIPSInst_FT(ir));
2167 DPFROMREG(fs, MIPSInst_FS(ir));
2168 rv.d = ieee754dp_fmax(fs, ft);
2169 break;
2170 }
2171
2172 case fmaxa_op: {
2173 union ieee754dp fs, ft;
2174
2175 if (!cpu_has_mips_r6)
2176 return SIGILL;
2177
2178 DPFROMREG(ft, MIPSInst_FT(ir));
2179 DPFROMREG(fs, MIPSInst_FS(ir));
2180 rv.d = ieee754dp_fmaxa(fs, ft);
2181 break;
2182 }
2183
2136 case fabs_op:
2137 handler.u = ieee754dp_abs;
2138 goto dcopuop;
2139
2140 case fneg_op:
2141 handler.u = ieee754dp_neg;
2142 goto dcopuop;
2143

--- 401 unchanged lines hidden --- 		2184 case fabs_op:
2185 handler.u = ieee754dp_abs;
2186 goto dcopuop;
2187
2188 case fneg_op:
2189 handler.u = ieee754dp_neg;
2190 goto dcopuop;
2191

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