| cp1emu.c (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) | cp1emu.c (edeed42402cebd9147b484d6df9964869bdc0681) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 4 * 5 * MIPS floating point support 6 * Copyright (C) 1994-2000 Algorithmics Ltd. 7 * 8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com --- 1018 unchanged lines hidden (view full) --- 1027 * FPU emulation code. 1028 * 1029 * NOTE: We cannot do this for branch instructions since they 1030 * are not a subset. Example: Cannot emulate a 16-bit 1031 * aligned target address with a MIPS32 instruction. 1032 */ 1033 if (dec_insn.micro_mips_mode) { 1034 /* | 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 4 * 5 * MIPS floating point support 6 * Copyright (C) 1994-2000 Algorithmics Ltd. 7 * 8 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com --- 1018 unchanged lines hidden (view full) --- 1027 * FPU emulation code. 1028 * 1029 * NOTE: We cannot do this for branch instructions since they 1030 * are not a subset. Example: Cannot emulate a 16-bit 1031 * aligned target address with a MIPS32 instruction. 1032 */ 1033 if (dec_insn.micro_mips_mode) { 1034 /* |
| 1035 * If next instruction is a 16-bit instruction, then it | 1035 * If next instruction is a 16-bit instruction, then |
| 1036 * it cannot be a FPU instruction. This could happen 1037 * since we can be called for non-FPU instructions. 1038 */ 1039 if ((pc_inc == 2) || 1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1041 == SIGILL)) 1042 return SIGILL; 1043 } --- 1905 unchanged lines hidden --- | 1036 * it cannot be a FPU instruction. This could happen 1037 * since we can be called for non-FPU instructions. 1038 */ 1039 if ((pc_inc == 2) || 1040 (microMIPS32_to_MIPS32((union mips_instruction *)&ir) 1041 == SIGILL)) 1042 return SIGILL; 1043 } --- 1905 unchanged lines hidden --- |