cp1emu.c (2cfcf8a8313bd9bdb54d62ca4ea581f130869aca) cp1emu.c (d4f5b088937e2dae7528245c597dcab7e57eb5f3)
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

--- 826 unchanged lines hidden (view full) ---

835} while (0)
836
837#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
838#define SPTOREG(sp, x) SITOREG((sp).bits, x)
839#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
840#define DPTOREG(dp, x) DITOREG((dp).bits, x)
841
842/*
1/*
2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
3 *
4 * MIPS floating point support
5 * Copyright (C) 1994-2000 Algorithmics Ltd.
6 *
7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
8 * Copyright (C) 2000 MIPS Technologies, Inc.

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835} while (0)
836
837#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
838#define SPTOREG(sp, x) SITOREG((sp).bits, x)
839#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
840#define DPTOREG(dp, x) DITOREG((dp).bits, x)
841
842/*
843 * Emulate a CFC1 instruction.
844 */
845static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
846 mips_instruction ir)
847{
848 u32 value;
849
850 if (MIPSInst_RD(ir) == FPCREG_CSR) {
851 value = ctx->fcr31;
852 pr_debug("%p gpr[%d]<-csr=%08x\n",
853 (void *)xcp->cp0_epc,
854 MIPSInst_RT(ir), value);
855 } else if (MIPSInst_RD(ir) == FPCREG_RID)
856 value = 0;
857 else
858 value = 0;
859 if (MIPSInst_RT(ir))
860 xcp->regs[MIPSInst_RT(ir)] = value;
861}
862
863/*
864 * Emulate a CTC1 instruction.
865 */
866static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
867 mips_instruction ir)
868{
869 u32 value;
870
871 if (MIPSInst_RT(ir) == 0)
872 value = 0;
873 else
874 value = xcp->regs[MIPSInst_RT(ir)];
875
876 /* we only have one writable control reg
877 */
878 if (MIPSInst_RD(ir) == FPCREG_CSR) {
879 pr_debug("%p gpr[%d]->csr=%08x\n",
880 (void *)xcp->cp0_epc,
881 MIPSInst_RT(ir), value);
882
883 /* Don't write reserved bits. */
884 ctx->fcr31 = value & ~FPU_CSR_RSVD;
885 }
886}
887
888/*
843 * Emulate the single floating point instruction pointed at by EPC.
844 * Two instructions if the instruction is in a branch delay slot.
845 */
846
847static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
848 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
849{
850 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
851 unsigned int cond, cbit;
852 mips_instruction ir;
853 int likely, pc_inc;
854 u32 __user *wva;
855 u64 __user *dva;
889 * Emulate the single floating point instruction pointed at by EPC.
890 * Two instructions if the instruction is in a branch delay slot.
891 */
892
893static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
894 struct mm_decoded_insn dec_insn, void *__user *fault_addr)
895{
896 unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
897 unsigned int cond, cbit;
898 mips_instruction ir;
899 int likely, pc_inc;
900 u32 __user *wva;
901 u64 __user *dva;
856 u32 value;
857 u32 wval;
858 u64 dval;
859 int sig;
860
861 /*
862 * These are giving gcc a gentle hint about what to expect in
863 * dec_inst in order to do better optimization.
864 */

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1041
1042 case mtc_op:
1043 /* copregister rd <- rt */
1044 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1045 break;
1046
1047 case cfc_op:
1048 /* cop control register rd -> gpr[rt] */
902 u32 wval;
903 u64 dval;
904 int sig;
905
906 /*
907 * These are giving gcc a gentle hint about what to expect in
908 * dec_inst in order to do better optimization.
909 */

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1086
1087 case mtc_op:
1088 /* copregister rd <- rt */
1089 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
1090 break;
1091
1092 case cfc_op:
1093 /* cop control register rd -> gpr[rt] */
1049 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1050 value = ctx->fcr31;
1051 pr_debug("%p gpr[%d]<-csr=%08x\n",
1052 (void *) (xcp->cp0_epc),
1053 MIPSInst_RT(ir), value);
1054 }
1055 else if (MIPSInst_RD(ir) == FPCREG_RID)
1056 value = 0;
1057 else
1058 value = 0;
1059 if (MIPSInst_RT(ir))
1060 xcp->regs[MIPSInst_RT(ir)] = value;
1094 cop1_cfc(xcp, ctx, ir);
1061 break;
1062
1063 case ctc_op:
1064 /* copregister rd <- rt */
1095 break;
1096
1097 case ctc_op:
1098 /* copregister rd <- rt */
1065 if (MIPSInst_RT(ir) == 0)
1066 value = 0;
1067 else
1068 value = xcp->regs[MIPSInst_RT(ir)];
1069
1070 /* we only have one writable control reg
1071 */
1072 if (MIPSInst_RD(ir) == FPCREG_CSR) {
1073 pr_debug("%p gpr[%d]->csr=%08x\n",
1074 (void *) (xcp->cp0_epc),
1075 MIPSInst_RT(ir), value);
1076
1077 /* Don't write reserved bits. */
1078 ctx->fcr31 = value & ~FPU_CSR_RSVD;
1079 }
1099 cop1_ctc(xcp, ctx, ir);
1080 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1081 return SIGFPE;
1082 }
1083 break;
1084
1085 case bc_op:
1086 if (delay_slot(xcp))
1087 return SIGILL;

--- 1009 unchanged lines hidden --- 		1100 if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
1101 return SIGFPE;
1102 }
1103 break;
1104
1105 case bc_op:
1106 if (delay_slot(xcp))
1107 return SIGILL;

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