| cp1emu.c (1c66b79bb3b11942a98085fd89295cf6cddae41a) | cp1emu.c (1b492600068d5fbd033196ce2bdb28735a23747e) |
|---|---|
| 1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. --- 613 unchanged lines hidden (view full) --- 622 *contpc = regs->cp0_epc + 623 dec_insn.pc_inc + 624 (insn.i_format.simmediate << 2); 625 else 626 *contpc = regs->cp0_epc + 627 dec_insn.pc_inc + 628 dec_insn.next_pc_inc; 629 return 1; | 1/* 2 * cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator 3 * 4 * MIPS floating point support 5 * Copyright (C) 1994-2000 Algorithmics Ltd. 6 * 7 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 8 * Copyright (C) 2000 MIPS Technologies, Inc. --- 613 unchanged lines hidden (view full) --- 622 *contpc = regs->cp0_epc + 623 dec_insn.pc_inc + 624 (insn.i_format.simmediate << 2); 625 else 626 *contpc = regs->cp0_epc + 627 dec_insn.pc_inc + 628 dec_insn.next_pc_inc; 629 return 1; |
| 630 case cbcond0_op: 631 case cbcond1_op: | 630 case pop10_op: 631 case pop30_op: |
| 632 if (!cpu_has_mips_r6) 633 break; 634 if (insn.i_format.rt && !insn.i_format.rs) 635 regs->regs[31] = regs->cp0_epc + 4; 636 *contpc = regs->cp0_epc + dec_insn.pc_inc + 637 dec_insn.next_pc_inc; 638 639 return 1; --- 1982 unchanged lines hidden --- | 632 if (!cpu_has_mips_r6) 633 break; 634 if (insn.i_format.rt && !insn.i_format.rs) 635 regs->regs[31] = regs->cp0_epc + 4; 636 *contpc = regs->cp0_epc + dec_insn.pc_inc + 637 dec_insn.next_pc_inc; 638 639 return 1; --- 1982 unchanged lines hidden --- |