| r4k_fpu.S (f26e8817b235d8764363bffcc9cbfc61867371f2) | r4k_fpu.S (a2aea699b1dde309f189ab41af41fae2d3345783) |
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| 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle 7 * 8 * Multi-arch abstraction and asm macros for easier reading: 9 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 10 * 11 * Carsten Langgaard, carstenl@mips.com 12 * Copyright (C) 2000 MIPS Technologies, Inc. 13 * Copyright (C) 1999, 2001 Silicon Graphics, Inc. 14 */ 15#include <asm/asm.h> 16#include <asm/asmmacro.h> 17#include <asm/errno.h> | 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle 7 * 8 * Multi-arch abstraction and asm macros for easier reading: 9 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 10 * 11 * Carsten Langgaard, carstenl@mips.com 12 * Copyright (C) 2000 MIPS Technologies, Inc. 13 * Copyright (C) 1999, 2001 Silicon Graphics, Inc. 14 */ 15#include <asm/asm.h> 16#include <asm/asmmacro.h> 17#include <asm/errno.h> |
| 18#include <asm/export.h> |
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| 18#include <asm/fpregdef.h> 19#include <asm/mipsregs.h> 20#include <asm/asm-offsets.h> 21#include <asm/regdef.h> 22 23/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 24#undef fp 25 26 .macro EX insn, reg, src 27 .set push 28 SET_HARDFLOAT 29 .set nomacro 30.ex\@: \insn \reg, \src 31 .set pop 32 .section __ex_table,"a" 33 PTR .ex\@, fault 34 .previous 35 .endm 36 | 19#include <asm/fpregdef.h> 20#include <asm/mipsregs.h> 21#include <asm/asm-offsets.h> 22#include <asm/regdef.h> 23 24/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ 25#undef fp 26 27 .macro EX insn, reg, src 28 .set push 29 SET_HARDFLOAT 30 .set nomacro 31.ex\@: \insn \reg, \src 32 .set pop 33 .section __ex_table,"a" 34 PTR .ex\@, fault 35 .previous 36 .endm 37 |
| 38/* 39 * Save a thread's fp context. 40 */ 41LEAF(_save_fp) 42EXPORT_SYMBOL(_save_fp) 43#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 44 defined(CONFIG_CPU_MIPS32_R6) 45 mfc0 t0, CP0_STATUS 46#endif 47 fpu_save_double a0 t0 t1 # clobbers t1 48 jr ra 49 END(_save_fp) 50 51/* 52 * Restore a thread's fp context. 53 */ 54LEAF(_restore_fp) 55#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2) || \ 56 defined(CONFIG_CPU_MIPS32_R6) 57 mfc0 t0, CP0_STATUS 58#endif 59 fpu_restore_double a0 t0 t1 # clobbers t1 60 jr ra 61 END(_restore_fp) 62 63#ifdef CONFIG_CPU_HAS_MSA 64 65/* 66 * Save a thread's MSA vector context. 67 */ 68LEAF(_save_msa) 69EXPORT_SYMBOL(_save_msa) 70 msa_save_all a0 71 jr ra 72 END(_save_msa) 73 74/* 75 * Restore a thread's MSA vector context. 76 */ 77LEAF(_restore_msa) 78 msa_restore_all a0 79 jr ra 80 END(_restore_msa) 81 82LEAF(_init_msa_upper) 83 msa_init_all_upper 84 jr ra 85 END(_init_msa_upper) 86 87#endif 88 89/* 90 * Load the FPU with signalling NANS. This bit pattern we're using has 91 * the property that no matter whether considered as single or as double 92 * precision represents signaling NANS. 93 * 94 * The value to initialize fcr31 to comes in $a0. 95 */ 96 97 .set push 98 SET_HARDFLOAT 99 100LEAF(_init_fpu) 101 mfc0 t0, CP0_STATUS 102 li t1, ST0_CU1 103 or t0, t1 104 mtc0 t0, CP0_STATUS 105 enable_fpu_hazard 106 107 ctc1 a0, fcr31 108 109 li t1, -1 # SNaN 110 111#ifdef CONFIG_64BIT 112 sll t0, t0, 5 113 bgez t0, 1f # 16 / 32 register mode? 114 115 dmtc1 t1, $f1 116 dmtc1 t1, $f3 117 dmtc1 t1, $f5 118 dmtc1 t1, $f7 119 dmtc1 t1, $f9 120 dmtc1 t1, $f11 121 dmtc1 t1, $f13 122 dmtc1 t1, $f15 123 dmtc1 t1, $f17 124 dmtc1 t1, $f19 125 dmtc1 t1, $f21 126 dmtc1 t1, $f23 127 dmtc1 t1, $f25 128 dmtc1 t1, $f27 129 dmtc1 t1, $f29 130 dmtc1 t1, $f31 1311: 132#endif 133 134#ifdef CONFIG_CPU_MIPS32 135 mtc1 t1, $f0 136 mtc1 t1, $f1 137 mtc1 t1, $f2 138 mtc1 t1, $f3 139 mtc1 t1, $f4 140 mtc1 t1, $f5 141 mtc1 t1, $f6 142 mtc1 t1, $f7 143 mtc1 t1, $f8 144 mtc1 t1, $f9 145 mtc1 t1, $f10 146 mtc1 t1, $f11 147 mtc1 t1, $f12 148 mtc1 t1, $f13 149 mtc1 t1, $f14 150 mtc1 t1, $f15 151 mtc1 t1, $f16 152 mtc1 t1, $f17 153 mtc1 t1, $f18 154 mtc1 t1, $f19 155 mtc1 t1, $f20 156 mtc1 t1, $f21 157 mtc1 t1, $f22 158 mtc1 t1, $f23 159 mtc1 t1, $f24 160 mtc1 t1, $f25 161 mtc1 t1, $f26 162 mtc1 t1, $f27 163 mtc1 t1, $f28 164 mtc1 t1, $f29 165 mtc1 t1, $f30 166 mtc1 t1, $f31 167 168#if defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_CPU_MIPS32_R6) 169 .set push 170 .set MIPS_ISA_LEVEL_RAW 171 .set fp=64 172 sll t0, t0, 5 # is Status.FR set? 173 bgez t0, 1f # no: skip setting upper 32b 174 175 mthc1 t1, $f0 176 mthc1 t1, $f1 177 mthc1 t1, $f2 178 mthc1 t1, $f3 179 mthc1 t1, $f4 180 mthc1 t1, $f5 181 mthc1 t1, $f6 182 mthc1 t1, $f7 183 mthc1 t1, $f8 184 mthc1 t1, $f9 185 mthc1 t1, $f10 186 mthc1 t1, $f11 187 mthc1 t1, $f12 188 mthc1 t1, $f13 189 mthc1 t1, $f14 190 mthc1 t1, $f15 191 mthc1 t1, $f16 192 mthc1 t1, $f17 193 mthc1 t1, $f18 194 mthc1 t1, $f19 195 mthc1 t1, $f20 196 mthc1 t1, $f21 197 mthc1 t1, $f22 198 mthc1 t1, $f23 199 mthc1 t1, $f24 200 mthc1 t1, $f25 201 mthc1 t1, $f26 202 mthc1 t1, $f27 203 mthc1 t1, $f28 204 mthc1 t1, $f29 205 mthc1 t1, $f30 206 mthc1 t1, $f31 2071: .set pop 208#endif /* CONFIG_CPU_MIPS32_R2 || CONFIG_CPU_MIPS32_R6 */ 209#else 210 .set MIPS_ISA_ARCH_LEVEL_RAW 211 dmtc1 t1, $f0 212 dmtc1 t1, $f2 213 dmtc1 t1, $f4 214 dmtc1 t1, $f6 215 dmtc1 t1, $f8 216 dmtc1 t1, $f10 217 dmtc1 t1, $f12 218 dmtc1 t1, $f14 219 dmtc1 t1, $f16 220 dmtc1 t1, $f18 221 dmtc1 t1, $f20 222 dmtc1 t1, $f22 223 dmtc1 t1, $f24 224 dmtc1 t1, $f26 225 dmtc1 t1, $f28 226 dmtc1 t1, $f30 227#endif 228 jr ra 229 END(_init_fpu) 230 231 .set pop /* SET_HARDFLOAT */ 232 |
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| 37 .set noreorder 38 39/** 40 * _save_fp_context() - save FP context from the FPU 41 * @a0 - pointer to fpregs field of sigcontext 42 * @a1 - pointer to fpc_csr field of sigcontext 43 * 44 * Save FP context, including the 32 FP data registers and the FP --- 321 unchanged lines hidden --- | 233 .set noreorder 234 235/** 236 * _save_fp_context() - save FP context from the FPU 237 * @a0 - pointer to fpregs field of sigcontext 238 * @a1 - pointer to fpc_csr field of sigcontext 239 * 240 * Save FP context, including the 32 FP data registers and the FP --- 321 unchanged lines hidden --- |