r4k_fpu.S (db985cbd67c45f875ef43cb5febfaa8cbd203c27) r4k_fpu.S (842dfc11ea9a21f9825167c8a4f2834b205b0a79)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
7 *
8 * Multi-arch abstraction and asm macros for easier reading:

--- 5 unchanged lines hidden (view full) ---

14 */
15#include <asm/asm.h>
16#include <asm/errno.h>
17#include <asm/fpregdef.h>
18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h>
20#include <asm/regdef.h>
21
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1996, 98, 99, 2000, 01 Ralf Baechle
7 *
8 * Multi-arch abstraction and asm macros for easier reading:

--- 5 unchanged lines hidden (view full) ---

14 */
15#include <asm/asm.h>
16#include <asm/errno.h>
17#include <asm/fpregdef.h>
18#include <asm/mipsregs.h>
19#include <asm/asm-offsets.h>
20#include <asm/regdef.h>
21
22/* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */
23#undef fp
24
22 .macro EX insn, reg, src
23 .set push
25 .macro EX insn, reg, src
26 .set push
27 SET_HARDFLOAT
24 .set nomacro
25.ex\@: \insn \reg, \src
26 .set pop
27 .section __ex_table,"a"
28 PTR .ex\@, fault
29 .previous
30 .endm
31
32 .set noreorder
33 .set arch=r4000
34
35LEAF(_save_fp_context)
28 .set nomacro
29.ex\@: \insn \reg, \src
30 .set pop
31 .section __ex_table,"a"
32 PTR .ex\@, fault
33 .previous
34 .endm
35
36 .set noreorder
37 .set arch=r4000
38
39LEAF(_save_fp_context)
40 .set push
41 SET_HARDFLOAT
36 cfc1 t1, fcr31
42 cfc1 t1, fcr31
43 .set pop
37
38#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
39 .set push
44
45#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
46 .set push
47 SET_HARDFLOAT
40#ifdef CONFIG_CPU_MIPS32_R2
48#ifdef CONFIG_CPU_MIPS32_R2
41 .set mips64r2
49 .set mips32r2
50 .set fp=64
42 mfc0 t0, CP0_STATUS
43 sll t0, t0, 5
44 bgez t0, 1f # skip storing odd if FR=0
45 nop
46#endif
47 /* Store the 16 odd double precision registers */
48 EX sdc1 $f1, SC_FPREGS+8(a0)
49 EX sdc1 $f3, SC_FPREGS+24(a0)

--- 9 unchanged lines hidden (view full) ---

59 EX sdc1 $f23, SC_FPREGS+184(a0)
60 EX sdc1 $f25, SC_FPREGS+200(a0)
61 EX sdc1 $f27, SC_FPREGS+216(a0)
62 EX sdc1 $f29, SC_FPREGS+232(a0)
63 EX sdc1 $f31, SC_FPREGS+248(a0)
641: .set pop
65#endif
66
51 mfc0 t0, CP0_STATUS
52 sll t0, t0, 5
53 bgez t0, 1f # skip storing odd if FR=0
54 nop
55#endif
56 /* Store the 16 odd double precision registers */
57 EX sdc1 $f1, SC_FPREGS+8(a0)
58 EX sdc1 $f3, SC_FPREGS+24(a0)

--- 9 unchanged lines hidden (view full) ---

68 EX sdc1 $f23, SC_FPREGS+184(a0)
69 EX sdc1 $f25, SC_FPREGS+200(a0)
70 EX sdc1 $f27, SC_FPREGS+216(a0)
71 EX sdc1 $f29, SC_FPREGS+232(a0)
72 EX sdc1 $f31, SC_FPREGS+248(a0)
731: .set pop
74#endif
75
76 .set push
77 SET_HARDFLOAT
67 /* Store the 16 even double precision registers */
68 EX sdc1 $f0, SC_FPREGS+0(a0)
69 EX sdc1 $f2, SC_FPREGS+16(a0)
70 EX sdc1 $f4, SC_FPREGS+32(a0)
71 EX sdc1 $f6, SC_FPREGS+48(a0)
72 EX sdc1 $f8, SC_FPREGS+64(a0)
73 EX sdc1 $f10, SC_FPREGS+80(a0)
74 EX sdc1 $f12, SC_FPREGS+96(a0)

--- 4 unchanged lines hidden (view full) ---

79 EX sdc1 $f22, SC_FPREGS+176(a0)
80 EX sdc1 $f24, SC_FPREGS+192(a0)
81 EX sdc1 $f26, SC_FPREGS+208(a0)
82 EX sdc1 $f28, SC_FPREGS+224(a0)
83 EX sdc1 $f30, SC_FPREGS+240(a0)
84 EX sw t1, SC_FPC_CSR(a0)
85 jr ra
86 li v0, 0 # success
78 /* Store the 16 even double precision registers */
79 EX sdc1 $f0, SC_FPREGS+0(a0)
80 EX sdc1 $f2, SC_FPREGS+16(a0)
81 EX sdc1 $f4, SC_FPREGS+32(a0)
82 EX sdc1 $f6, SC_FPREGS+48(a0)
83 EX sdc1 $f8, SC_FPREGS+64(a0)
84 EX sdc1 $f10, SC_FPREGS+80(a0)
85 EX sdc1 $f12, SC_FPREGS+96(a0)

--- 4 unchanged lines hidden (view full) ---

90 EX sdc1 $f22, SC_FPREGS+176(a0)
91 EX sdc1 $f24, SC_FPREGS+192(a0)
92 EX sdc1 $f26, SC_FPREGS+208(a0)
93 EX sdc1 $f28, SC_FPREGS+224(a0)
94 EX sdc1 $f30, SC_FPREGS+240(a0)
95 EX sw t1, SC_FPC_CSR(a0)
96 jr ra
97 li v0, 0 # success
98 .set pop
87 END(_save_fp_context)
88
89#ifdef CONFIG_MIPS32_COMPAT
90 /* Save 32-bit process floating point context */
91LEAF(_save_fp_context32)
99 END(_save_fp_context)
100
101#ifdef CONFIG_MIPS32_COMPAT
102 /* Save 32-bit process floating point context */
103LEAF(_save_fp_context32)
104 .set push
105 SET_HARDFLOAT
92 cfc1 t1, fcr31
93
94 mfc0 t0, CP0_STATUS
95 sll t0, t0, 5
96 bgez t0, 1f # skip storing odd if FR=0
97 nop
98
99 /* Store the 16 odd double precision registers */

--- 29 unchanged lines hidden (view full) ---

129 EX sdc1 $f22, SC32_FPREGS+176(a0)
130 EX sdc1 $f24, SC32_FPREGS+192(a0)
131 EX sdc1 $f26, SC32_FPREGS+208(a0)
132 EX sdc1 $f28, SC32_FPREGS+224(a0)
133 EX sdc1 $f30, SC32_FPREGS+240(a0)
134 EX sw t1, SC32_FPC_CSR(a0)
135 cfc1 t0, $0 # implementation/version
136 EX sw t0, SC32_FPC_EIR(a0)
106 cfc1 t1, fcr31
107
108 mfc0 t0, CP0_STATUS
109 sll t0, t0, 5
110 bgez t0, 1f # skip storing odd if FR=0
111 nop
112
113 /* Store the 16 odd double precision registers */

--- 29 unchanged lines hidden (view full) ---

143 EX sdc1 $f22, SC32_FPREGS+176(a0)
144 EX sdc1 $f24, SC32_FPREGS+192(a0)
145 EX sdc1 $f26, SC32_FPREGS+208(a0)
146 EX sdc1 $f28, SC32_FPREGS+224(a0)
147 EX sdc1 $f30, SC32_FPREGS+240(a0)
148 EX sw t1, SC32_FPC_CSR(a0)
149 cfc1 t0, $0 # implementation/version
150 EX sw t0, SC32_FPC_EIR(a0)
151 .set pop
137
138 jr ra
139 li v0, 0 # success
140 END(_save_fp_context32)
141#endif
142
143/*
144 * Restore FPU state:
145 * - fp gp registers
146 * - cp1 status/control register
147 */
148LEAF(_restore_fp_context)
149 EX lw t1, SC_FPC_CSR(a0)
150
151#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
152 .set push
152
153 jr ra
154 li v0, 0 # success
155 END(_save_fp_context32)
156#endif
157
158/*
159 * Restore FPU state:
160 * - fp gp registers
161 * - cp1 status/control register
162 */
163LEAF(_restore_fp_context)
164 EX lw t1, SC_FPC_CSR(a0)
165
166#if defined(CONFIG_64BIT) || defined(CONFIG_CPU_MIPS32_R2)
167 .set push
168 SET_HARDFLOAT
153#ifdef CONFIG_CPU_MIPS32_R2
169#ifdef CONFIG_CPU_MIPS32_R2
154 .set mips64r2
170 .set mips32r2
171 .set fp=64
155 mfc0 t0, CP0_STATUS
156 sll t0, t0, 5
157 bgez t0, 1f # skip loading odd if FR=0
158 nop
159#endif
160 EX ldc1 $f1, SC_FPREGS+8(a0)
161 EX ldc1 $f3, SC_FPREGS+24(a0)
162 EX ldc1 $f5, SC_FPREGS+40(a0)

--- 7 unchanged lines hidden (view full) ---

170 EX ldc1 $f21, SC_FPREGS+168(a0)
171 EX ldc1 $f23, SC_FPREGS+184(a0)
172 EX ldc1 $f25, SC_FPREGS+200(a0)
173 EX ldc1 $f27, SC_FPREGS+216(a0)
174 EX ldc1 $f29, SC_FPREGS+232(a0)
175 EX ldc1 $f31, SC_FPREGS+248(a0)
1761: .set pop
177#endif
172 mfc0 t0, CP0_STATUS
173 sll t0, t0, 5
174 bgez t0, 1f # skip loading odd if FR=0
175 nop
176#endif
177 EX ldc1 $f1, SC_FPREGS+8(a0)
178 EX ldc1 $f3, SC_FPREGS+24(a0)
179 EX ldc1 $f5, SC_FPREGS+40(a0)

--- 7 unchanged lines hidden (view full) ---

187 EX ldc1 $f21, SC_FPREGS+168(a0)
188 EX ldc1 $f23, SC_FPREGS+184(a0)
189 EX ldc1 $f25, SC_FPREGS+200(a0)
190 EX ldc1 $f27, SC_FPREGS+216(a0)
191 EX ldc1 $f29, SC_FPREGS+232(a0)
192 EX ldc1 $f31, SC_FPREGS+248(a0)
1931: .set pop
194#endif
195 .set push
196 SET_HARDFLOAT
178 EX ldc1 $f0, SC_FPREGS+0(a0)
179 EX ldc1 $f2, SC_FPREGS+16(a0)
180 EX ldc1 $f4, SC_FPREGS+32(a0)
181 EX ldc1 $f6, SC_FPREGS+48(a0)
182 EX ldc1 $f8, SC_FPREGS+64(a0)
183 EX ldc1 $f10, SC_FPREGS+80(a0)
184 EX ldc1 $f12, SC_FPREGS+96(a0)
185 EX ldc1 $f14, SC_FPREGS+112(a0)
186 EX ldc1 $f16, SC_FPREGS+128(a0)
187 EX ldc1 $f18, SC_FPREGS+144(a0)
188 EX ldc1 $f20, SC_FPREGS+160(a0)
189 EX ldc1 $f22, SC_FPREGS+176(a0)
190 EX ldc1 $f24, SC_FPREGS+192(a0)
191 EX ldc1 $f26, SC_FPREGS+208(a0)
192 EX ldc1 $f28, SC_FPREGS+224(a0)
193 EX ldc1 $f30, SC_FPREGS+240(a0)
194 ctc1 t1, fcr31
197 EX ldc1 $f0, SC_FPREGS+0(a0)
198 EX ldc1 $f2, SC_FPREGS+16(a0)
199 EX ldc1 $f4, SC_FPREGS+32(a0)
200 EX ldc1 $f6, SC_FPREGS+48(a0)
201 EX ldc1 $f8, SC_FPREGS+64(a0)
202 EX ldc1 $f10, SC_FPREGS+80(a0)
203 EX ldc1 $f12, SC_FPREGS+96(a0)
204 EX ldc1 $f14, SC_FPREGS+112(a0)
205 EX ldc1 $f16, SC_FPREGS+128(a0)
206 EX ldc1 $f18, SC_FPREGS+144(a0)
207 EX ldc1 $f20, SC_FPREGS+160(a0)
208 EX ldc1 $f22, SC_FPREGS+176(a0)
209 EX ldc1 $f24, SC_FPREGS+192(a0)
210 EX ldc1 $f26, SC_FPREGS+208(a0)
211 EX ldc1 $f28, SC_FPREGS+224(a0)
212 EX ldc1 $f30, SC_FPREGS+240(a0)
213 ctc1 t1, fcr31
214 .set pop
195 jr ra
196 li v0, 0 # success
197 END(_restore_fp_context)
198
199#ifdef CONFIG_MIPS32_COMPAT
200LEAF(_restore_fp_context32)
201 /* Restore an o32 sigcontext. */
215 jr ra
216 li v0, 0 # success
217 END(_restore_fp_context)
218
219#ifdef CONFIG_MIPS32_COMPAT
220LEAF(_restore_fp_context32)
221 /* Restore an o32 sigcontext. */
222 .set push
223 SET_HARDFLOAT
202 EX lw t1, SC32_FPC_CSR(a0)
203
204 mfc0 t0, CP0_STATUS
205 sll t0, t0, 5
206 bgez t0, 1f # skip loading odd if FR=0
207 nop
208
209 EX ldc1 $f1, SC32_FPREGS+8(a0)

--- 27 unchanged lines hidden (view full) ---

237 EX ldc1 $f22, SC32_FPREGS+176(a0)
238 EX ldc1 $f24, SC32_FPREGS+192(a0)
239 EX ldc1 $f26, SC32_FPREGS+208(a0)
240 EX ldc1 $f28, SC32_FPREGS+224(a0)
241 EX ldc1 $f30, SC32_FPREGS+240(a0)
242 ctc1 t1, fcr31
243 jr ra
244 li v0, 0 # success
224 EX lw t1, SC32_FPC_CSR(a0)
225
226 mfc0 t0, CP0_STATUS
227 sll t0, t0, 5
228 bgez t0, 1f # skip loading odd if FR=0
229 nop
230
231 EX ldc1 $f1, SC32_FPREGS+8(a0)

--- 27 unchanged lines hidden (view full) ---

259 EX ldc1 $f22, SC32_FPREGS+176(a0)
260 EX ldc1 $f24, SC32_FPREGS+192(a0)
261 EX ldc1 $f26, SC32_FPREGS+208(a0)
262 EX ldc1 $f28, SC32_FPREGS+224(a0)
263 EX ldc1 $f30, SC32_FPREGS+240(a0)
264 ctc1 t1, fcr31
265 jr ra
266 li v0, 0 # success
267 .set pop
245 END(_restore_fp_context32)
246#endif
247
248 .set reorder
249
250 .type fault@function
251 .ent fault
252fault: li v0, -EFAULT # failure
253 jr ra
254 .end fault
268 END(_restore_fp_context32)
269#endif
270
271 .set reorder
272
273 .type fault@function
274 .ent fault
275fault: li v0, -EFAULT # failure
276 jr ra
277 .end fault