| octeon_switch.S (38fd2c202a3d82bc12430bce5789fa2c2a406f71) | octeon_switch.S (a36d8225bceba4b7be47ade34d175945f85cffbc) |
|---|---|
| 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 * written by Carsten Langgaard, carstenl@mips.com 12 */ | 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle 7 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse 9 * Copyright (C) 1999 Silicon Graphics, Inc. 10 * Copyright (C) 2000 MIPS Technologies, Inc. 11 * written by Carsten Langgaard, carstenl@mips.com 12 */ |
| 13#include <asm/asm.h> 14#include <asm/cachectl.h> 15#include <asm/fpregdef.h> 16#include <asm/mipsregs.h> 17#include <asm/asm-offsets.h> 18#include <asm/pgtable-bits.h> 19#include <asm/regdef.h> 20#include <asm/stackframe.h> 21#include <asm/thread_info.h> | |
| 22 | 13 |
| 23#include <asm/asmmacro.h> 24 | 14#define USE_ALTERNATE_RESUME_IMPL 1 15 .set push 16 .set arch=mips64r2 17#include "r4k_switch.S" 18 .set pop |
| 25/* | 19/* |
| 26 * Offset to the current process status flags, the first 32 bytes of the 27 * stack are not used. 28 */ 29#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) 30 31/* | |
| 32 * task_struct *resume(task_struct *prev, task_struct *next, 33 * struct thread_info *next_ti, int usedfpu) 34 */ 35 .align 7 36 LEAF(resume) 37 .set arch=octeon 38 mfc0 t1, CP0_STATUS 39 LONG_S t1, THREAD_STATUS(a0) 40 cpu_save_nonscratch a0 41 LONG_S ra, THREAD_REG31(a0) 42 | 20 * task_struct *resume(task_struct *prev, task_struct *next, 21 * struct thread_info *next_ti, int usedfpu) 22 */ 23 .align 7 24 LEAF(resume) 25 .set arch=octeon 26 mfc0 t1, CP0_STATUS 27 LONG_S t1, THREAD_STATUS(a0) 28 cpu_save_nonscratch a0 29 LONG_S ra, THREAD_REG31(a0) 30 |
| 31 /* 32 * check if we need to save FPU registers 33 */ 34 PTR_L t3, TASK_THREAD_INFO(a0) 35 LONG_L t0, TI_FLAGS(t3) 36 li t1, _TIF_USEDFPU 37 and t2, t0, t1 38 beqz t2, 1f 39 nor t1, zero, t1 40 41 and t0, t0, t1 42 LONG_S t0, TI_FLAGS(t3) 43 44 /* 45 * clear saved user stack CU1 bit 46 */ 47 LONG_L t0, ST_OFF(t3) 48 li t1, ~ST0_CU1 49 and t0, t0, t1 50 LONG_S t0, ST_OFF(t3) 51 52 .set push 53 .set arch=mips64r2 54 fpu_save_double a0 t0 t1 # c0_status passed in t0 55 # clobbers t1 56 .set pop 571: 58 59 /* check if we need to save COP2 registers */ 60 PTR_L t2, TASK_THREAD_INFO(a0) 61 LONG_L t0, ST_OFF(t2) 62 bbit0 t0, 30, 1f 63 64 /* Disable COP2 in the stored process state */ 65 li t1, ST0_CU2 66 xor t0, t1 67 LONG_S t0, ST_OFF(t2) 68 69 /* Enable COP2 so we can save it */ 70 mfc0 t0, CP0_STATUS 71 or t0, t1 72 mtc0 t0, CP0_STATUS 73 74 /* Save COP2 */ 75 daddu a0, THREAD_CP2 76 jal octeon_cop2_save 77 dsubu a0, THREAD_CP2 78 79 /* Disable COP2 now that we are done */ 80 mfc0 t0, CP0_STATUS 81 li t1, ST0_CU2 82 xor t0, t1 83 mtc0 t0, CP0_STATUS 84 851: |
|
| 43#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 44 /* Check if we need to store CVMSEG state */ 45 mfc0 t0, $11,7 /* CvmMemCtl */ 46 bbit0 t0, 6, 3f /* Is user access enabled? */ 47 48 /* Store the CVMSEG state */ 49 /* Extract the size of CVMSEG */ 50 andi t0, 0x3f --- 29 unchanged lines hidden (view full) --- 80 81 /* 82 * The order of restoring the registers takes care of the race 83 * updating $28, $29 and kernelsp without disabling ints. 84 */ 85 move $28, a2 86 cpu_restore_nonscratch a1 87 | 86#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 87 /* Check if we need to store CVMSEG state */ 88 mfc0 t0, $11,7 /* CvmMemCtl */ 89 bbit0 t0, 6, 3f /* Is user access enabled? */ 90 91 /* Store the CVMSEG state */ 92 /* Extract the size of CVMSEG */ 93 andi t0, 0x3f --- 29 unchanged lines hidden (view full) --- 123 124 /* 125 * The order of restoring the registers takes care of the race 126 * updating $28, $29 and kernelsp without disabling ints. 127 */ 128 move $28, a2 129 cpu_restore_nonscratch a1 130 |
| 88#if (_THREAD_SIZE - 32) < 0x8000 89 PTR_ADDIU t0, $28, _THREAD_SIZE - 32 90#else 91 PTR_LI t0, _THREAD_SIZE - 32 92 PTR_ADDU t0, $28 93#endif | 131 PTR_ADDU t0, $28, _THREAD_SIZE - 32 |
| 94 set_saved_sp t0, t1, t2 95 96 mfc0 t1, CP0_STATUS /* Do we really need this? */ 97 li a3, 0xff01 98 and t1, a3 99 LONG_L a2, THREAD_STATUS(a1) 100 nor a3, $0, a3 101 and a2, a3 --- 380 unchanged lines hidden --- | 132 set_saved_sp t0, t1, t2 133 134 mfc0 t1, CP0_STATUS /* Do we really need this? */ 135 li a3, 0xff01 136 and t1, a3 137 LONG_L a2, THREAD_STATUS(a1) 138 nor a3, $0, a3 139 and a2, a3 --- 380 unchanged lines hidden --- |