irq-msc01.c (513b046c96cc2fbce730a3474f6f7ff0c4fdd05c) irq-msc01.c (1603b5aca4f15b34848fb5594d0c7b6333b99144)
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com

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40{
41 if (irq < (irq_base + 32))
42 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
43 else
44 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
45}
46
47/*
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License as published by the
4 * Free Software Foundation; either version 2 of the License, or (at your
5 * option) any later version.
6 *
7 * Copyright (c) 2004 MIPS Inc
8 * Author: chris@mips.com

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40{
41 if (irq < (irq_base + 32))
42 MSCIC_WRITE(MSC01_IC_ENAL, 1<<(irq - irq_base));
43 else
44 MSCIC_WRITE(MSC01_IC_ENAH, 1<<(irq - irq_base - 32));
45}
46
47/*
48 * Enables the IRQ on SOC-it
49 */
50static void enable_msc_irq(unsigned int irq)
51{
52 unmask_msc_irq(irq);
53}
54
55/*
56 * Initialize the IRQ on SOC-it
57 */
58static unsigned int startup_msc_irq(unsigned int irq)
59{
60 unmask_msc_irq(irq);
61 return 0;
62}
63
64/*
65 * Disables the IRQ on SOC-it
66 */
67static void disable_msc_irq(unsigned int irq)
68{
69 mask_msc_irq(irq);
70}
71
72/*
73 * Masks and ACKs an IRQ
74 */
75static void level_mask_and_ack_msc_irq(unsigned int irq)
76{
77 mask_msc_irq(irq);
78 if (!cpu_has_veic)
79 MSCIC_WRITE(MSC01_IC_EOI, 0);
80#ifdef CONFIG_MIPS_MT_SMTC

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131
132void
133msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
134{
135 MSCIC_WRITE(MSC01_IC_RAMW,
136 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
137}
138
48 * Masks and ACKs an IRQ
49 */
50static void level_mask_and_ack_msc_irq(unsigned int irq)
51{
52 mask_msc_irq(irq);
53 if (!cpu_has_veic)
54 MSCIC_WRITE(MSC01_IC_EOI, 0);
55#ifdef CONFIG_MIPS_MT_SMTC

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106
107void
108msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
109{
110 MSCIC_WRITE(MSC01_IC_RAMW,
111 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
112}
113
139#define shutdown_msc_irq disable_msc_irq
140
141struct irq_chip msc_levelirq_type = {
142 .typename = "SOC-it-Level",
114struct irq_chip msc_levelirq_type = {
115 .typename = "SOC-it-Level",
143 .startup = startup_msc_irq,
144 .shutdown = shutdown_msc_irq,
145 .enable = enable_msc_irq,
146 .disable = disable_msc_irq,
147 .ack = level_mask_and_ack_msc_irq,
116 .ack = level_mask_and_ack_msc_irq,
117 .mask = mask_msc_irq,
118 .mask_ack = level_mask_and_ack_msc_irq,
119 .unmask = unmask_msc_irq,
148 .end = end_msc_irq,
149};
150
151struct irq_chip msc_edgeirq_type = {
152 .typename = "SOC-it-Edge",
120 .end = end_msc_irq,
121};
122
123struct irq_chip msc_edgeirq_type = {
124 .typename = "SOC-it-Edge",
153 .startup =startup_msc_irq,
154 .shutdown = shutdown_msc_irq,
155 .enable = enable_msc_irq,
156 .disable = disable_msc_irq,
157 .ack = edge_mask_and_ack_msc_irq,
125 .ack = edge_mask_and_ack_msc_irq,
126 .mask = mask_msc_irq,
127 .mask_ack = edge_mask_and_ack_msc_irq,
128 .unmask = unmask_msc_irq,
158 .end = end_msc_irq,
159};
160
161
162void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
163{
164 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
165

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170
171 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
172
173 for (; nirq >= 0; nirq--, imp++) {
174 int n = imp->im_irq;
175
176 switch (imp->im_type) {
177 case MSC01_IRQ_EDGE:
129 .end = end_msc_irq,
130};
131
132
133void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
134{
135 extern void (*board_bind_eic_interrupt)(unsigned int irq, unsigned int regset);
136

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141
142 board_bind_eic_interrupt = &msc_bind_eic_interrupt;
143
144 for (; nirq >= 0; nirq--, imp++) {
145 int n = imp->im_irq;
146
147 switch (imp->im_type) {
148 case MSC01_IRQ_EDGE:
178 irq_desc[base+n].chip = &msc_edgeirq_type;
149 set_irq_chip(base+n, &msc_edgeirq_type);
179 if (cpu_has_veic)
180 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
181 else
182 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
183 break;
184 case MSC01_IRQ_LEVEL:
150 if (cpu_has_veic)
151 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
152 else
153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
154 break;
155 case MSC01_IRQ_LEVEL:
185 irq_desc[base+n].chip = &msc_levelirq_type;
156 set_irq_chip(base+n, &msc_levelirq_type);
186 if (cpu_has_veic)
187 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
188 else
189 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
190 }
191 }
192
193 irq_base = base;
194
195 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
196
197}
157 if (cpu_has_veic)
158 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
159 else
160 MSCIC_WRITE(MSC01_IC_SUP+n*8, imp->im_lvl);
161 }
162 }
163
164 irq_base = base;
165
166 MSCIC_WRITE(MSC01_IC_GENA, MSC01_IC_GENA_GENA_BIT); /* Enable interrupt generation */
167
168}