| bmips_vec.S (cbbda6e7c9c3e4532bd70a73ff9d5e6655c894dc) | bmips_vec.S (21b30c00f3067001519eda166675c1958b163c91) |
|---|---|
| 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7 * 8 * Reset/NMI/re-entry vectors for BMIPS processors --- 74 unchanged lines hidden (view full) --- 83 .set noat 84 .align 4 85 86#ifdef CONFIG_SMP 87 /* if the NMI bit is clear, assume this is a CPU1 reset instead */ 88 li k1, (1 << 19) 89 mfc0 k0, CP0_STATUS 90 and k0, k1 | 1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com) 7 * 8 * Reset/NMI/re-entry vectors for BMIPS processors --- 74 unchanged lines hidden (view full) --- 83 .set noat 84 .align 4 85 86#ifdef CONFIG_SMP 87 /* if the NMI bit is clear, assume this is a CPU1 reset instead */ 88 li k1, (1 << 19) 89 mfc0 k0, CP0_STATUS 90 and k0, k1 |
| 91 beqz k0, bmips_smp_entry | 91 beqz k0, soft_reset |
| 92 93#if defined(CONFIG_CPU_BMIPS5000) 94 mfc0 k0, CP0_PRID 95 li k1, PRID_IMP_BMIPS5000 96 /* mask with PRID_IMP_BMIPS5000 to cover both variants */ 97 andi k0, PRID_IMP_BMIPS5000 98 bne k0, k1, 1f 99 --- 21 unchanged lines hidden (view full) --- 121 /* jump to the NMI handler function */ 122 la k0, nmi_handler 123 jr k0 124 125 RESTORE_ALL 126 .set arch=r4000 127 eret 128 | 92 93#if defined(CONFIG_CPU_BMIPS5000) 94 mfc0 k0, CP0_PRID 95 li k1, PRID_IMP_BMIPS5000 96 /* mask with PRID_IMP_BMIPS5000 to cover both variants */ 97 andi k0, PRID_IMP_BMIPS5000 98 bne k0, k1, 1f 99 --- 21 unchanged lines hidden (view full) --- 121 /* jump to the NMI handler function */ 122 la k0, nmi_handler 123 jr k0 124 125 RESTORE_ALL 126 .set arch=r4000 127 eret 128 |
| 129#ifdef CONFIG_SMP 130soft_reset: 131 132#if defined(CONFIG_CPU_BMIPS5000) 133 mfc0 k0, CP0_PRID 134 andi k0, 0xff00 135 li k1, PRID_IMP_BMIPS5200 136 bne k0, k1, bmips_smp_entry 137 138 /* if running on TP 1, jump to bmips_smp_entry */ 139 mfc0 k0, $22 140 li k1, (1 << 24) 141 and k1, k0 142 bnez k1, bmips_smp_entry 143 nop 144 145 /* 146 * running on TP0, can not be core 0 (the boot core). 147 * Check for soft reset. Indicates a warm boot 148 */ 149 mfc0 k0, $12 150 li k1, (1 << 20) 151 and k0, k1 152 beqz k0, bmips_smp_entry 153 154 /* 155 * Warm boot. 156 * Cache init is only done on TP0 157 */ 158 la k0, bmips_5xxx_init 159 jalr k0 160 nop 161 162 b bmips_smp_entry 163 nop 164#endif 165 |
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| 129/*********************************************************************** 130 * CPU1 reset vector (used for the initial boot only) 131 * This is still part of bmips_reset_nmi_vec(). 132 ***********************************************************************/ 133 | 166/*********************************************************************** 167 * CPU1 reset vector (used for the initial boot only) 168 * This is still part of bmips_reset_nmi_vec(). 169 ***********************************************************************/ 170 |
| 134#ifdef CONFIG_SMP 135 | |
| 136bmips_smp_entry: 137 138 /* set up CP0 STATUS; enable FPU */ 139 li k0, 0x30000000 140 mtc0 k0, CP0_STATUS 141 BARRIER 142 143 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */ --- 144 unchanged lines hidden --- | 171bmips_smp_entry: 172 173 /* set up CP0 STATUS; enable FPU */ 174 li k0, 0x30000000 175 mtc0 k0, CP0_STATUS 176 BARRIER 177 178 /* set local CP0 CONFIG to make kseg0 cacheable, write-back */ --- 144 unchanged lines hidden --- |