sync.h (8dd06ef34b6e2f41b29fbf5fc1663780f2524285) sync.h (2f9060b1db4aa2c21c248e34476d8936a2b69cf6)
1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef __MIPS_ASM_SYNC_H__
3#define __MIPS_ASM_SYNC_H__
4
5/*
6 * sync types are defined by the MIPS64 Instruction Set documentation in Volume
7 * II-A of the MIPS Architecture Reference Manual, which can be found here:
8 *

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14 * completed & often involve stalling the CPU pipeline to do so.
15 *
16 * 2) Ordering barriers, which only ensure that affected memory operations
17 * won't be reordered in the CPU pipeline in a manner that violates the
18 * restrictions imposed by the barrier.
19 *
20 * Ordering barriers can be more efficient than completion barriers, since:
21 *
1/* SPDX-License-Identifier: GPL-2.0-only */
2#ifndef __MIPS_ASM_SYNC_H__
3#define __MIPS_ASM_SYNC_H__
4
5/*
6 * sync types are defined by the MIPS64 Instruction Set documentation in Volume
7 * II-A of the MIPS Architecture Reference Manual, which can be found here:
8 *

--- 5 unchanged lines hidden (view full) ---

14 * completed & often involve stalling the CPU pipeline to do so.
15 *
16 * 2) Ordering barriers, which only ensure that affected memory operations
17 * won't be reordered in the CPU pipeline in a manner that violates the
18 * restrictions imposed by the barrier.
19 *
20 * Ordering barriers can be more efficient than completion barriers, since:
21 *
22 * a) Ordering barriers only require memory access instructions which preceed
22 * a) Ordering barriers only require memory access instructions which precede
23 * them in program order (older instructions) to reach a point in the
24 * load/store datapath beyond which reordering is not possible before
25 * allowing memory access instructions which follow them (younger
26 * instructions) to be performed. That is, older instructions don't
27 * actually need to complete - they just need to get far enough that all
28 * other coherent CPUs will observe their completion before they observe
29 * the effects of younger instructions.
30 *

--- 179 unchanged lines hidden --- 		23 * them in program order (older instructions) to reach a point in the
24 * load/store datapath beyond which reordering is not possible before
25 * allowing memory access instructions which follow them (younger
26 * instructions) to be performed. That is, older instructions don't
27 * actually need to complete - they just need to get far enough that all
28 * other coherent CPUs will observe their completion before they observe
29 * the effects of younger instructions.
30 *

--- 179 unchanged lines hidden ---