fpu.h (65844bb0a7861eefa3ce44cd788163ecc4e14f2d) fpu.h (9b26616c8d9dae53fbac7f7cb2c6dd1308102976)
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.

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25
26#ifdef CONFIG_MIPS_MT_FPAFF
27#include <asm/mips_mt.h>
28#endif
29
30struct sigcontext;
31struct sigcontext32;
32
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.

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25
26#ifdef CONFIG_MIPS_MT_FPAFF
27#include <asm/mips_mt.h>
28#endif
29
30struct sigcontext;
31struct sigcontext32;
32
33extern void _init_fpu(void);
33extern void _init_fpu(unsigned int);
34extern void _save_fp(struct task_struct *);
35extern void _restore_fp(struct task_struct *);
36
37/*
38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully matches the desired value of the Status.FR bit.
41 */
42enum fpu_mode {
43 FPU_32BIT = 0, /* FR = 0 */
44 FPU_64BIT, /* FR = 1, FRE = 0 */
45 FPU_AS_IS,
46 FPU_HYBRID, /* FR = 1, FRE = 1 */
47
48#define FPU_FR_MASK 0x1
49};
50
34extern void _save_fp(struct task_struct *);
35extern void _restore_fp(struct task_struct *);
36
37/*
38 * This enum specifies a mode in which we want the FPU to operate, for cores
39 * which implement the Status.FR bit. Note that the bottom bit of the value
40 * purposefully matches the desired value of the Status.FR bit.
41 */
42enum fpu_mode {
43 FPU_32BIT = 0, /* FR = 0 */
44 FPU_64BIT, /* FR = 1, FRE = 0 */
45 FPU_AS_IS,
46 FPU_HYBRID, /* FR = 1, FRE = 1 */
47
48#define FPU_FR_MASK 0x1
49};
50
51#define __disable_fpu() \
52do { \
53 clear_c0_status(ST0_CU1); \
54 disable_fpu_hazard(); \
55} while (0)
56
57static inline int __enable_fpu(enum fpu_mode mode)
58{
59 int fr;
60
61 switch (mode) {
62 case FPU_AS_IS:
63 /* just enable the FPU in its current mode */
64 set_c0_status(ST0_CU1);

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87 }
88fr_common:
89 /* set CU1 & change FR appropriately */
90 fr = (int)mode & FPU_FR_MASK;
91 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
92 enable_fpu_hazard();
93
94 /* check FR has the desired value */
51static inline int __enable_fpu(enum fpu_mode mode)
52{
53 int fr;
54
55 switch (mode) {
56 case FPU_AS_IS:
57 /* just enable the FPU in its current mode */
58 set_c0_status(ST0_CU1);

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81 }
82fr_common:
83 /* set CU1 & change FR appropriately */
84 fr = (int)mode & FPU_FR_MASK;
85 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
86 enable_fpu_hazard();
87
88 /* check FR has the desired value */
95 if (!!(read_c0_status() & ST0_FR) == !!fr)
96 return 0;
89 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;
97
90
98 /* unsupported FR value */
99 __disable_fpu();
100 return SIGFPE;
101
102 default:
103 BUG();
104 }
105
106 return SIGFPE;
107}
108
91 default:
92 BUG();
93 }
94
95 return SIGFPE;
96}
97
98#define __disable_fpu() \
99do { \
100 clear_c0_status(ST0_CU1); \
101 disable_fpu_hazard(); \
102} while (0)
103
109#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
110
111static inline int __is_fpu_owner(void)
112{
113 return test_thread_flag(TIF_USEDFPU);
114}
115
116static inline int is_fpu_owner(void)

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170 if (is_msa_enabled()) {
171 if (save) {
172 save_msa(current);
173 current->thread.fpu.fcr31 =
174 read_32bit_cp1_register(CP1_STATUS);
175 }
176 disable_msa();
177 clear_thread_flag(TIF_USEDMSA);
104#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
105
106static inline int __is_fpu_owner(void)
107{
108 return test_thread_flag(TIF_USEDFPU);
109}
110
111static inline int is_fpu_owner(void)

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165 if (is_msa_enabled()) {
166 if (save) {
167 save_msa(current);
168 current->thread.fpu.fcr31 =
169 read_32bit_cp1_register(CP1_STATUS);
170 }
171 disable_msa();
172 clear_thread_flag(TIF_USEDMSA);
178 __disable_fpu();
179 } else if (is_fpu_owner()) {
180 if (save)
181 _save_fp(current);
182 __disable_fpu();
183 }
184 KSTK_STATUS(current) &= ~ST0_CU1;
185 clear_thread_flag(TIF_USEDFPU);
186 preempt_enable();
187}
188
189static inline int init_fpu(void)
190{
173 } else if (is_fpu_owner()) {
174 if (save)
175 _save_fp(current);
176 __disable_fpu();
177 }
178 KSTK_STATUS(current) &= ~ST0_CU1;
179 clear_thread_flag(TIF_USEDFPU);
180 preempt_enable();
181}
182
183static inline int init_fpu(void)
184{
185 unsigned int fcr31 = current->thread.fpu.fcr31;
191 int ret = 0;
192
193 if (cpu_has_fpu) {
194 unsigned int config5;
195
196 ret = __own_fpu();
197 if (ret)
198 return ret;
199
200 if (!cpu_has_fre) {
186 int ret = 0;
187
188 if (cpu_has_fpu) {
189 unsigned int config5;
190
191 ret = __own_fpu();
192 if (ret)
193 return ret;
194
195 if (!cpu_has_fre) {
201 _init_fpu();
196 _init_fpu(fcr31);
202
203 return 0;
204 }
205
206 /*
207 * Ensure FRE is clear whilst running _init_fpu, since
208 * single precision FP instructions are used. If FRE
209 * was set then we'll just end up initialising all 32
210 * 64b registers.
211 */
212 config5 = clear_c0_config5(MIPS_CONF5_FRE);
213 enable_fpu_hazard();
214
197
198 return 0;
199 }
200
201 /*
202 * Ensure FRE is clear whilst running _init_fpu, since
203 * single precision FP instructions are used. If FRE
204 * was set then we'll just end up initialising all 32
205 * 64b registers.
206 */
207 config5 = clear_c0_config5(MIPS_CONF5_FRE);
208 enable_fpu_hazard();
209
215 _init_fpu();
210 _init_fpu(fcr31);
216
217 /* Restore FRE */
218 write_c0_config5(config5);
219 enable_fpu_hazard();
220 } else
221 fpu_emulator_init_fpu();
222
223 return ret;

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212 /* Restore FRE */
213 write_c0_config5(config5);
214 enable_fpu_hazard();
215 } else
216 fpu_emulator_init_fpu();
217
218 return ret;

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