fpu.h (0a87a2db485a1456b7427914969c0e8195a1bbda) fpu.h (b0c34f6155e2d8bbe096a85a770d63ee6be6c726)
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.

--- 60 unchanged lines hidden (view full) ---

69
70 case FPU_64BIT:
71#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
72 /* we only have a 32-bit FPU */
73 return SIGFPE;
74#endif
75 /* fall through */
76 case FPU_32BIT:
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.

--- 60 unchanged lines hidden (view full) ---

69
70 case FPU_64BIT:
71#if !(defined(CONFIG_CPU_MIPS32_R2) || defined(CONFIG_64BIT))
72 /* we only have a 32-bit FPU */
73 return SIGFPE;
74#endif
75 /* fall through */
76 case FPU_32BIT:
77 /* clear FRE */
78 write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
77 if (cpu_has_fre) {
78 /* clear FRE */
79 write_c0_config5(read_c0_config5() & ~MIPS_CONF5_FRE);
80 }
79fr_common:
80 /* set CU1 & change FR appropriately */
81 fr = (int)mode & FPU_FR_MASK;
82 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
83 enable_fpu_hazard();
84
85 /* check FR has the desired value */
86 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;

--- 90 unchanged lines hidden (view full) ---

177 preempt_enable();
178}
179
180static inline int init_fpu(void)
181{
182 int ret = 0;
183
184 if (cpu_has_fpu) {
81fr_common:
82 /* set CU1 & change FR appropriately */
83 fr = (int)mode & FPU_FR_MASK;
84 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
85 enable_fpu_hazard();
86
87 /* check FR has the desired value */
88 return (!!(read_c0_status() & ST0_FR) == !!fr) ? 0 : SIGFPE;

--- 90 unchanged lines hidden (view full) ---

179 preempt_enable();
180}
181
182static inline int init_fpu(void)
183{
184 int ret = 0;
185
186 if (cpu_has_fpu) {
187 unsigned int config5;
188
185 ret = __own_fpu();
189 ret = __own_fpu();
186 if (!ret) {
187 unsigned int config5 = read_c0_config5();
190 if (ret)
191 return ret;
188
192
189 /*
190 * Ensure FRE is clear whilst running _init_fpu, since
191 * single precision FP instructions are used. If FRE
192 * was set then we'll just end up initialising all 32
193 * 64b registers.
194 */
195 write_c0_config5(config5 & ~MIPS_CONF5_FRE);
196 enable_fpu_hazard();
197
193 if (!cpu_has_fre) {
198 _init_fpu();
199
194 _init_fpu();
195
200 /* Restore FRE */
201 write_c0_config5(config5);
202 enable_fpu_hazard();
196 return 0;
203 }
197 }
198
199 config5 = read_c0_config5();
200
201 /*
202 * Ensure FRE is clear whilst running _init_fpu, since
203 * single precision FP instructions are used. If FRE
204 * was set then we'll just end up initialising all 32
205 * 64b registers.
206 */
207 write_c0_config5(config5 & ~MIPS_CONF5_FRE);
208 enable_fpu_hazard();
209
210 _init_fpu();
211
212 /* Restore FRE */
213 write_c0_config5(config5);
214 enable_fpu_hazard();
204 } else
205 fpu_emulator_init_fpu();
206
207 return ret;
208}
209
210static inline void save_fp(struct task_struct *tsk)
211{

--- 23 unchanged lines hidden --- 		215 } else
216 fpu_emulator_init_fpu();
217
218 return ret;
219}
220
221static inline void save_fp(struct task_struct *tsk)
222{

--- 23 unchanged lines hidden ---