| kn05.h (55fa518867978e1f5fd8353098f80d125ac734d7) | kn05.h (fd28b9ac8e8944b04ace0fceb7222edd4e42b00a) |
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| 1/* 2 * include/asm-mips/dec/kn05.h 3 * 4 * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min 5 * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or 6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC 7 * definitions. 8 * --- 35 unchanged lines hidden (view full) --- 44#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ 45#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ 46#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 47#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ 48#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ 49#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 50 51/* | 1/* 2 * include/asm-mips/dec/kn05.h 3 * 4 * DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min 5 * or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or 6 * KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC 7 * definitions. 8 * --- 35 unchanged lines hidden (view full) --- 44#define KN4K_RES_10 (10*IOASIC_SLOT_SIZE) /* unused? */ 45#define KN4K_RES_11 (11*IOASIC_SLOT_SIZE) /* unused? */ 46#define KN4K_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */ 47#define KN4K_RES_13 (13*IOASIC_SLOT_SIZE) /* unused? */ 48#define KN4K_RES_14 (14*IOASIC_SLOT_SIZE) /* unused? */ 49#define KN4K_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */ 50 51/* |
| 52 * MB ASIC interrupt bits. 53 */ 54#define KN4K_MB_INR_MB 4 /* ??? */ 55#define KN4K_MB_INR_MT 3 /* memory, I/O bus read/write errors */ 56#define KN4K_MB_INR_RES_2 2 /* unused */ 57#define KN4K_MB_INR_RTC 1 /* RTC */ 58#define KN4K_MB_INR_TC 0 /* I/O ASIC cascade */ 59 60/* |
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| 52 * Bits for the MB interrupt register. 53 * The register appears read-only. 54 */ | 61 * Bits for the MB interrupt register. 62 * The register appears read-only. 63 */ |
| 55#define KN4K_MB_INT_TC (1<<0) /* TURBOchannel? */ 56#define KN4K_MB_INT_RTC (1<<1) /* RTC? */ 57#define KN4K_MB_INT_MT (1<<3) /* I/O ASIC cascade */ | 64#define KN4K_MB_INT_IRQ (0x1f<<0) /* CPU Int[4:0] status. */ 65#define KN4K_MB_INT_IRQ_N(n) (1<<(n)) /* Individual status bits. */ |
| 58 59/* 60 * Bits for the MB control & status register. 61 * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. 62 */ 63#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ 64#define KN4K_MB_CSR_F (1<<1) /* ??? */ 65#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ 66#define KN4K_MB_CSR_OD (1<<10) /* ??? */ 67#define KN4K_MB_CSR_CP (1<<11) /* ??? */ 68#define KN4K_MB_CSR_UNC (1<<12) /* ??? */ 69#define KN4K_MB_CSR_IM (1<<13) /* ??? */ 70#define KN4K_MB_CSR_NC (1<<14) /* ??? */ 71#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 72#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ | 66 67/* 68 * Bits for the MB control & status register. 69 * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware. 70 */ 71#define KN4K_MB_CSR_PF (1<<0) /* PreFetching enable? */ 72#define KN4K_MB_CSR_F (1<<1) /* ??? */ 73#define KN4K_MB_CSR_ECC (0xff<<2) /* ??? */ 74#define KN4K_MB_CSR_OD (1<<10) /* ??? */ 75#define KN4K_MB_CSR_CP (1<<11) /* ??? */ 76#define KN4K_MB_CSR_UNC (1<<12) /* ??? */ 77#define KN4K_MB_CSR_IM (1<<13) /* ??? */ 78#define KN4K_MB_CSR_NC (1<<14) /* ??? */ 79#define KN4K_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */ 80#define KN4K_MB_CSR_MSK (0x1f<<16) /* CPU Int[4:0] mask */ |
| 81#define KN4K_MB_CSR_MSK_N(n) (1<<((n)+16)) /* Individual mask bits. */ |
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| 73#define KN4K_MB_CSR_FW (1<<21) /* ??? */ 74#define KN4K_MB_CSR_W (1<<31) /* ??? */ 75 76#endif /* __ASM_MIPS_DEC_KN05_H */ | 82#define KN4K_MB_CSR_FW (1<<21) /* ??? */ 83#define KN4K_MB_CSR_W (1<<31) /* ??? */ 84 85#endif /* __ASM_MIPS_DEC_KN05_H */ |