| cpu.h (1bdd3e05a0a3b4a97ea88bc46fef8fb265c8b94c) | cpu.h (ece276de2a1f90b6a7836d388c372b9025345469) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * cpu.h: Values of the PRId register used to match up 4 * various MIPS cpu types. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 2004, 2013 Maciej W. Rozycki 8 */ --- 32 unchanged lines hidden (view full) --- 41#define PRID_COMP_SANDCRAFT 0x050000 42#define PRID_COMP_NXP 0x060000 43#define PRID_COMP_TOSHIBA 0x070000 44#define PRID_COMP_LSI 0x080000 45#define PRID_COMP_LEXRA 0x0b0000 46#define PRID_COMP_NETLOGIC 0x0c0000 47#define PRID_COMP_CAVIUM 0x0d0000 48#define PRID_COMP_LOONGSON 0x140000 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * cpu.h: Values of the PRId register used to match up 4 * various MIPS cpu types. 5 * 6 * Copyright (C) 1996 David S. Miller (davem@davemloft.net) 7 * Copyright (C) 2004, 2013 Maciej W. Rozycki 8 */ --- 32 unchanged lines hidden (view full) --- 41#define PRID_COMP_SANDCRAFT 0x050000 42#define PRID_COMP_NXP 0x060000 43#define PRID_COMP_TOSHIBA 0x070000 44#define PRID_COMP_LSI 0x080000 45#define PRID_COMP_LEXRA 0x0b0000 46#define PRID_COMP_NETLOGIC 0x0c0000 47#define PRID_COMP_CAVIUM 0x0d0000 48#define PRID_COMP_LOONGSON 0x140000 |
| 49#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750 */ | 49#define PRID_COMP_INGENIC_D0 0xd00000 /* JZ4740, JZ4750, X1830 */ |
| 50#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */ 51#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ 52 53/* 54 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 55 * register. In order to detect a certain CPU type exactly eventually 56 * additional registers may need to be examined. 57 */ --- 122 unchanged lines hidden (view full) --- 180#define PRID_IMP_CAVIUM_CN70XX 0x9600 181#define PRID_IMP_CAVIUM_CN73XX 0x9700 182#define PRID_IMP_CAVIUM_CNF75XX 0x9800 183 184/* 185 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* 186 */ 187 | 50#define PRID_COMP_INGENIC_D1 0xd10000 /* JZ4770, JZ4775, X1000 */ 51#define PRID_COMP_INGENIC_E1 0xe10000 /* JZ4780 */ 52 53/* 54 * Assigned Processor ID (implementation) values for bits 15:8 of the PRId 55 * register. In order to detect a certain CPU type exactly eventually 56 * additional registers may need to be examined. 57 */ --- 122 unchanged lines hidden (view full) --- 180#define PRID_IMP_CAVIUM_CN70XX 0x9600 181#define PRID_IMP_CAVIUM_CN73XX 0x9700 182#define PRID_IMP_CAVIUM_CNF75XX 0x9800 183 184/* 185 * These are the PRID's for when 23:16 == PRID_COMP_INGENIC_* 186 */ 187 |
| 188#define PRID_IMP_XBURST 0x0200 | 188#define PRID_IMP_XBURST_REV1 0x0200 /* XBurst with MXU SIMD ISA */ 189#define PRID_IMP_XBURST_REV2 0x0100 /* XBurst with MXU2 SIMD ISA */ |
| 189 190/* 191 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 192 */ 193#define PRID_IMP_NETLOGIC_XLR732 0x0000 194#define PRID_IMP_NETLOGIC_XLR716 0x0200 195#define PRID_IMP_NETLOGIC_XLR532 0x0900 196#define PRID_IMP_NETLOGIC_XLR308 0x0600 --- 213 unchanged lines hidden (view full) --- 410#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */ 411#define MIPS_CPU_SHARED_FTLB_RAM \ 412 BIT_ULL(54) /* CPU shares FTLB RAM with another */ 413#define MIPS_CPU_SHARED_FTLB_ENTRIES \ 414 BIT_ULL(55) /* CPU shares FTLB entries with another */ 415#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \ 416 BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */ 417#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */ | 190 191/* 192 * These are the PRID's for when 23:16 == PRID_COMP_NETLOGIC 193 */ 194#define PRID_IMP_NETLOGIC_XLR732 0x0000 195#define PRID_IMP_NETLOGIC_XLR716 0x0200 196#define PRID_IMP_NETLOGIC_XLR532 0x0900 197#define PRID_IMP_NETLOGIC_XLR308 0x0600 --- 213 unchanged lines hidden (view full) --- 411#define MIPS_CPU_UFR BIT_ULL(53) /* CPU supports User mode FR switching */ 412#define MIPS_CPU_SHARED_FTLB_RAM \ 413 BIT_ULL(54) /* CPU shares FTLB RAM with another */ 414#define MIPS_CPU_SHARED_FTLB_ENTRIES \ 415 BIT_ULL(55) /* CPU shares FTLB entries with another */ 416#define MIPS_CPU_MT_PER_TC_PERF_COUNTERS \ 417 BIT_ULL(56) /* CPU has perf counters implemented per TC (MIPSMT ASE) */ 418#define MIPS_CPU_MMID BIT_ULL(57) /* CPU supports MemoryMapIDs */ |
| 419#define MIPS_CPU_MAC_2008_ONLY BIT_ULL(58) /* CPU Only support MAC2008 Fused multiply-add instruction */ |
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| 418 419/* 420 * CPU ASE encodings 421 */ 422#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 423#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 424#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 425#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ --- 13 unchanged lines hidden --- | 420 421/* 422 * CPU ASE encodings 423 */ 424#define MIPS_ASE_MIPS16 0x00000001 /* code compression */ 425#define MIPS_ASE_MDMX 0x00000002 /* MIPS digital media extension */ 426#define MIPS_ASE_MIPS3D 0x00000004 /* MIPS-3D */ 427#define MIPS_ASE_SMARTMIPS 0x00000008 /* SmartMIPS */ --- 13 unchanged lines hidden --- |