irq.c (4e45171c4e31578157189ca22cfb7b2bcc5f69f2) irq.c (d5ab1a6910fe850fa092888f210cf6c43136a7ab)
1/*
2 * IRQ vector handles
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15
16#include <asm/i8259.h>
17#include <asm/irq_cpu.h>
1/*
2 * IRQ vector handles
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 2003 by Ralf Baechle
9 */
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/irq.h>
13#include <linux/interrupt.h>
14#include <linux/pci.h>
15
16#include <asm/i8259.h>
17#include <asm/irq_cpu.h>
18#include <asm/irq_gt641xx.h>
18#include <asm/gt64120.h>
19
19#include <asm/gt64120.h>
20
20#include <cobalt.h>
21#include <irq.h>
21
22
22/*
23 * We have two types of interrupts that we handle, ones that come in through
24 * the CPU interrupt lines, and ones that come in on the via chip. The CPU
25 * mappings are:
26 *
27 * 16 - Software interrupt 0 (unused) IE_SW0
28 * 17 - Software interrupt 1 (unused) IE_SW1
29 * 18 - Galileo chip (timer) IE_IRQ0
30 * 19 - Tulip 0 + NCR SCSI IE_IRQ1
31 * 20 - Tulip 1 IE_IRQ2
32 * 21 - 16550 UART IE_IRQ3
33 * 22 - VIA southbridge PIC IE_IRQ4
34 * 23 - unused IE_IRQ5
35 *
36 * The VIA chip is a master/slave 8259 setup and has the following interrupts:
37 *
38 * 8 - RTC
39 * 9 - PCI
40 * 14 - IDE0
41 * 15 - IDE1
42 */
43
44static inline void galileo_irq(void)
23asmlinkage void plat_irq_dispatch(void)
45{
24{
46 unsigned int mask, pending, devfn;
47
48 mask = GT_READ(GT_INTRMASK_OFS);
49 pending = GT_READ(GT_INTRCAUSE_OFS) & mask;
50
51 if (pending & GT_INTR_T0EXP_MSK) {
52 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_T0EXP_MSK);
53 do_IRQ(COBALT_GALILEO_IRQ);
54 } else if (pending & GT_INTR_RETRYCTR0_MSK) {
55 devfn = GT_READ(GT_PCI0_CFGADDR_OFS) >> 8;
56 GT_WRITE(GT_INTRCAUSE_OFS, ~GT_INTR_RETRYCTR0_MSK);
57 printk(KERN_WARNING
58 "Galileo: PCI retry count exceeded (%02x.%u)\n",
59 PCI_SLOT(devfn), PCI_FUNC(devfn));
60 } else {
61 GT_WRITE(GT_INTRMASK_OFS, mask & ~pending);
62 printk(KERN_WARNING
63 "Galileo: masking unexpected interrupt %08x\n", pending);
64 }
65}
66
67static inline void via_pic_irq(void)
68{
25 unsigned pending = read_c0_status() & read_c0_cause() & ST0_IM;
69 int irq;
70
26 int irq;
27
71 irq = i8259_irq();
72 if (irq >= 0)
73 do_IRQ(irq);
28 if (pending & CAUSEF_IP2)
29 gt641xx_irq_dispatch();
30 else if (pending & CAUSEF_IP6) {
31 irq = i8259_irq();
32 if (irq < 0)
33 spurious_interrupt();
34 else
35 do_IRQ(irq);
36 } else if (pending & CAUSEF_IP3)
37 do_IRQ(MIPS_CPU_IRQ_BASE + 3);
38 else if (pending & CAUSEF_IP4)
39 do_IRQ(MIPS_CPU_IRQ_BASE + 4);
40 else if (pending & CAUSEF_IP5)
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5);
42 else if (pending & CAUSEF_IP7)
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
44 else
45 spurious_interrupt();
74}
75
46}
47
76asmlinkage void plat_irq_dispatch(void)
77{
78 unsigned pending = read_c0_status() & read_c0_cause();
79
80 if (pending & CAUSEF_IP2) /* COBALT_GALILEO_IRQ (18) */
81 galileo_irq();
82 else if (pending & CAUSEF_IP6) /* COBALT_VIA_IRQ (22) */
83 via_pic_irq();
84 else if (pending & CAUSEF_IP3) /* COBALT_ETH0_IRQ (19) */
85 do_IRQ(COBALT_CPU_IRQ + 3);
86 else if (pending & CAUSEF_IP4) /* COBALT_ETH1_IRQ (20) */
87 do_IRQ(COBALT_CPU_IRQ + 4);
88 else if (pending & CAUSEF_IP5) /* COBALT_SERIAL_IRQ (21) */
89 do_IRQ(COBALT_CPU_IRQ + 5);
90 else if (pending & CAUSEF_IP7) /* IRQ 23 */
91 do_IRQ(COBALT_CPU_IRQ + 7);
92}
93
94static struct irqaction irq_via = {
95 .handler = no_action,
96 .mask = CPU_MASK_NONE,
97 .name = "cascade"
48static struct irqaction cascade = {
49 .handler = no_action,
50 .mask = CPU_MASK_NONE,
51 .name = "cascade",
98};
99
100void __init arch_init_irq(void)
101{
52};
53
54void __init arch_init_irq(void)
55{
102 /*
103 * Mask all Galileo interrupts. The Galileo
104 * handler is set in cobalt_timer_setup()
105 */
106 GT_WRITE(GT_INTRMASK_OFS, 0);
56 mips_cpu_irq_init();
57 gt641xx_irq_init();
58 init_i8259_irqs();
107
59
108 init_i8259_irqs(); /* 0 ... 15 */
109 mips_cpu_irq_init(); /* 16 ... 23 */
110
111 /*
112 * Mask all cpu interrupts
113 * (except IE4, we already masked those at VIA level)
114 */
115 change_c0_status(ST0_IM, IE_IRQ4);
116
117 setup_irq(COBALT_VIA_IRQ, &irq_via);
60 setup_irq(GT641XX_CASCADE_IRQ, &cascade);
61 setup_irq(I8259_CASCADE_IRQ, &cascade);
118}
62}