bcm7362.dtsi (cfc8be04c36a1a6546b6f9cb8f02fd9f215c9d38) bcm7362.dtsi (a2c510a2d0418ce15cd739d0a177ce53b06e5695)
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7362";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;

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21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
1/ {
2 #address-cells = <1>;
3 #size-cells = <1>;
4 compatible = "brcm,bcm7362";
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;

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21 reg = <1>;
22 };
23 };
24
25 aliases {
26 uart0 = &uart0;
27 };
28
29 cpu_intc: cpu_intc {
29 cpu_intc: interrupt-controller {
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {

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50
51 rdb {
52 #address-cells = <1>;
53 #size-cells = <1>;
54
55 compatible = "simple-bus";
56 ranges = <0 0x10000000 0x01000000>;
57
30 #address-cells = <0>;
31 compatible = "mti,cpu-interrupt-controller";
32
33 interrupt-controller;
34 #interrupt-cells = <1>;
35 };
36
37 clocks {

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50
51 rdb {
52 #address-cells = <1>;
53 #size-cells = <1>;
54
55 compatible = "simple-bus";
56 ranges = <0 0x10000000 0x01000000>;
57
58 periph_intc: periph_intc@411400 {
58 periph_intc: interrupt-controller@411400 {
59 compatible = "brcm,bcm7038-l1-intc";
60 reg = <0x411400 0x30>, <0x411600 0x30>;
61
62 interrupt-controller;
63 #interrupt-cells = <1>;
64
65 interrupt-parent = <&cpu_intc>;
66 interrupts = <2>, <3>;
67 };
68
59 compatible = "brcm,bcm7038-l1-intc";
60 reg = <0x411400 0x30>, <0x411600 0x30>;
61
62 interrupt-controller;
63 #interrupt-cells = <1>;
64
65 interrupt-parent = <&cpu_intc>;
66 interrupts = <2>, <3>;
67 };
68
69 sun_l2_intc: sun_l2_intc@403000 {
69 sun_l2_intc: interrupt-controller@403000 {
70 compatible = "brcm,l2-intc";
71 reg = <0x403000 0x30>;
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 interrupt-parent = <&periph_intc>;
75 interrupts = <48>;
76 };
77

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82 interrupt-parent = <&sun_l2_intc>;
83 interrupts = <0>, <2>;
84 brcm,gisb-arb-master-mask = <0x2f3>;
85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
86 "rdc_0", "raaga_0",
87 "avd_0", "jtag_0";
88 };
89
70 compatible = "brcm,l2-intc";
71 reg = <0x403000 0x30>;
72 interrupt-controller;
73 #interrupt-cells = <1>;
74 interrupt-parent = <&periph_intc>;
75 interrupts = <48>;
76 };
77

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82 interrupt-parent = <&sun_l2_intc>;
83 interrupts = <0>, <2>;
84 brcm,gisb-arb-master-mask = <0x2f3>;
85 brcm,gisb-arb-master-names = "ssp_0", "cpu_0", "bsp_0",
86 "rdc_0", "raaga_0",
87 "avd_0", "jtag_0";
88 };
89
90 upg_irq0_intc: upg_irq0_intc@406600 {
90 upg_irq0_intc: interrupt-controller@406600 {
91 compatible = "brcm,bcm7120-l2-intc";
92 reg = <0x406600 0x8>;
93
94 brcm,int-map-mask = <0x44>, <0x7000000>;
95 brcm,int-fwd-mask = <0x70000>;
96
97 interrupt-controller;
98 #interrupt-cells = <1>;
99
100 interrupt-parent = <&periph_intc>;
101 interrupts = <56>, <54>;
102 interrupt-names = "upg_main", "upg_bsc";
103 };
104
91 compatible = "brcm,bcm7120-l2-intc";
92 reg = <0x406600 0x8>;
93
94 brcm,int-map-mask = <0x44>, <0x7000000>;
95 brcm,int-fwd-mask = <0x70000>;
96
97 interrupt-controller;
98 #interrupt-cells = <1>;
99
100 interrupt-parent = <&periph_intc>;
101 interrupts = <56>, <54>;
102 interrupt-names = "upg_main", "upg_bsc";
103 };
104
105 upg_aon_irq0_intc: upg_aon_irq0_intc@408b80 {
105 upg_aon_irq0_intc: interrupt-controller@408b80 {
106 compatible = "brcm,bcm7120-l2-intc";
107 reg = <0x408b80 0x8>;
108
109 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
110 brcm,int-fwd-mask = <0>;
111 brcm,irq-can-wake;
112
113 interrupt-controller;

--- 245 unchanged lines hidden --- 		106 compatible = "brcm,bcm7120-l2-intc";
107 reg = <0x408b80 0x8>;
108
109 brcm,int-map-mask = <0x40>, <0x8000000>, <0x100000>;
110 brcm,int-fwd-mask = <0>;
111 brcm,irq-can-wake;
112
113 interrupt-controller;

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