reset.c (bf61c8840efe60fd8f91446860b63338fb424158) reset.c (2c8aaf71b0a4738ae8cb70d9367089bdb892aea3)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
7 */
8

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80#define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
81#define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
82#define BCM6358_RESET_ENETSW 0
83#define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
84#define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
85#define BCM6358_RESET_PCIE 0
86#define BCM6358_RESET_PCIE_EXT 0
87
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2012 Jonas Gorski <jonas.gorski@gmail.com>
7 */
8

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80#define BCM6358_RESET_SAR SOFTRESET_6358_SAR_MASK
81#define BCM6358_RESET_EPHY SOFTRESET_6358_EPHY_MASK
82#define BCM6358_RESET_ENETSW 0
83#define BCM6358_RESET_PCM SOFTRESET_6358_PCM_MASK
84#define BCM6358_RESET_MPI SOFTRESET_6358_MPI_MASK
85#define BCM6358_RESET_PCIE 0
86#define BCM6358_RESET_PCIE_EXT 0
87
88#define BCM6362_RESET_SPI SOFTRESET_6362_SPI_MASK
89#define BCM6362_RESET_ENET 0
90#define BCM6362_RESET_USBH SOFTRESET_6362_USBH_MASK
91#define BCM6362_RESET_USBD SOFTRESET_6362_USBS_MASK
92#define BCM6362_RESET_DSL 0
93#define BCM6362_RESET_SAR SOFTRESET_6362_SAR_MASK
94#define BCM6362_RESET_EPHY SOFTRESET_6362_EPHY_MASK
95#define BCM6362_RESET_ENETSW SOFTRESET_6362_ENETSW_MASK
96#define BCM6362_RESET_PCM SOFTRESET_6362_PCM_MASK
97#define BCM6362_RESET_MPI 0
98#define BCM6362_RESET_PCIE (SOFTRESET_6362_PCIE_MASK | \
99 SOFTRESET_6362_PCIE_CORE_MASK)
100#define BCM6362_RESET_PCIE_EXT SOFTRESET_6362_PCIE_EXT_MASK
101
88#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
89#define BCM6368_RESET_ENET 0
90#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
91#define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
92#define BCM6368_RESET_DSL 0
93#define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
94#define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
95#define BCM6368_RESET_ENETSW 0

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114static const u32 bcm6348_reset_bits[] = {
115 __GEN_RESET_BITS_TABLE(6348)
116};
117
118static const u32 bcm6358_reset_bits[] = {
119 __GEN_RESET_BITS_TABLE(6358)
120};
121
102#define BCM6368_RESET_SPI SOFTRESET_6368_SPI_MASK
103#define BCM6368_RESET_ENET 0
104#define BCM6368_RESET_USBH SOFTRESET_6368_USBH_MASK
105#define BCM6368_RESET_USBD SOFTRESET_6368_USBS_MASK
106#define BCM6368_RESET_DSL 0
107#define BCM6368_RESET_SAR SOFTRESET_6368_SAR_MASK
108#define BCM6368_RESET_EPHY SOFTRESET_6368_EPHY_MASK
109#define BCM6368_RESET_ENETSW 0

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128static const u32 bcm6348_reset_bits[] = {
129 __GEN_RESET_BITS_TABLE(6348)
130};
131
132static const u32 bcm6358_reset_bits[] = {
133 __GEN_RESET_BITS_TABLE(6358)
134};
135
136static const u32 bcm6362_reset_bits[] = {
137 __GEN_RESET_BITS_TABLE(6362)
138};
139
122static const u32 bcm6368_reset_bits[] = {
123 __GEN_RESET_BITS_TABLE(6368)
124};
125
126const u32 *bcm63xx_reset_bits;
127static int reset_reg;
128
129static int __init bcm63xx_reset_bits_init(void)

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135 reset_reg = PERF_SOFTRESET_REG;
136 bcm63xx_reset_bits = bcm6338_reset_bits;
137 } else if (BCMCPU_IS_6348()) {
138 reset_reg = PERF_SOFTRESET_REG;
139 bcm63xx_reset_bits = bcm6348_reset_bits;
140 } else if (BCMCPU_IS_6358()) {
141 reset_reg = PERF_SOFTRESET_6358_REG;
142 bcm63xx_reset_bits = bcm6358_reset_bits;
140static const u32 bcm6368_reset_bits[] = {
141 __GEN_RESET_BITS_TABLE(6368)
142};
143
144const u32 *bcm63xx_reset_bits;
145static int reset_reg;
146
147static int __init bcm63xx_reset_bits_init(void)

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153 reset_reg = PERF_SOFTRESET_REG;
154 bcm63xx_reset_bits = bcm6338_reset_bits;
155 } else if (BCMCPU_IS_6348()) {
156 reset_reg = PERF_SOFTRESET_REG;
157 bcm63xx_reset_bits = bcm6348_reset_bits;
158 } else if (BCMCPU_IS_6358()) {
159 reset_reg = PERF_SOFTRESET_6358_REG;
160 bcm63xx_reset_bits = bcm6358_reset_bits;
161 } else if (BCMCPU_IS_6362()) {
162 reset_reg = PERF_SOFTRESET_6362_REG;
163 bcm63xx_reset_bits = bcm6362_reset_bits;
143 } else if (BCMCPU_IS_6368()) {
144 reset_reg = PERF_SOFTRESET_6368_REG;
145 bcm63xx_reset_bits = bcm6368_reset_bits;
146 }
147
148 return 0;
149}
150#else

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177
178#ifdef CONFIG_BCM63XX_CPU_6358
179static const u32 bcm63xx_reset_bits[] = {
180 __GEN_RESET_BITS_TABLE(6358)
181};
182#define reset_reg PERF_SOFTRESET_6358_REG
183#endif
184
164 } else if (BCMCPU_IS_6368()) {
165 reset_reg = PERF_SOFTRESET_6368_REG;
166 bcm63xx_reset_bits = bcm6368_reset_bits;
167 }
168
169 return 0;
170}
171#else

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198
199#ifdef CONFIG_BCM63XX_CPU_6358
200static const u32 bcm63xx_reset_bits[] = {
201 __GEN_RESET_BITS_TABLE(6358)
202};
203#define reset_reg PERF_SOFTRESET_6358_REG
204#endif
205
206#ifdef CONFIG_BCM63XX_CPU_6362
207static const u32 bcm63xx_reset_bits[] = {
208 __GEN_RESET_BITS_TABLE(6362)
209};
210#define reset_reg PERF_SOFTRESET_6362_REG
211#endif
212
185#ifdef CONFIG_BCM63XX_CPU_6368
186static const u32 bcm63xx_reset_bits[] = {
187 __GEN_RESET_BITS_TABLE(6368)
188};
189#define reset_reg PERF_SOFTRESET_6368_REG
190#endif
191
192static int __init bcm63xx_reset_bits_init(void) { return 0; }

--- 31 unchanged lines hidden --- 		213#ifdef CONFIG_BCM63XX_CPU_6368
214static const u32 bcm63xx_reset_bits[] = {
215 __GEN_RESET_BITS_TABLE(6368)
216};
217#define reset_reg PERF_SOFTRESET_6368_REG
218#endif
219
220static int __init bcm63xx_reset_bits_init(void) { return 0; }

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