cpu.c (288752a8aa1be6cf89ee5066435a617efd97fb86) cpu.c (e5766aea5b9b7519654261c27b639f567b5415b4)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */

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24const int *bcm63xx_irqs;
25EXPORT_SYMBOL(bcm63xx_irqs);
26
27static u16 bcm63xx_cpu_id;
28static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size;
31
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */

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24const int *bcm63xx_irqs;
25EXPORT_SYMBOL(bcm63xx_irqs);
26
27static u16 bcm63xx_cpu_id;
28static u16 bcm63xx_cpu_rev;
29static unsigned int bcm63xx_cpu_freq;
30static unsigned int bcm63xx_memory_size;
31
32static const unsigned long bcm6328_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6328)
34};
35
36static const int bcm6328_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(6328)
38};
39
32static const unsigned long bcm6338_regs_base[] = {
33 __GEN_CPU_REGS_TABLE(6338)
34};
35
36static const int bcm6338_irqs[] = {
37 __GEN_CPU_IRQ_TABLE(6338)
38};
39

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94unsigned int bcm63xx_get_memory_size(void)
95{
96 return bcm63xx_memory_size;
97}
98
99static unsigned int detect_cpu_clock(void)
100{
101 switch (bcm63xx_get_cpu_id()) {
40static const unsigned long bcm6338_regs_base[] = {
41 __GEN_CPU_REGS_TABLE(6338)
42};
43
44static const int bcm6338_irqs[] = {
45 __GEN_CPU_IRQ_TABLE(6338)
46};
47

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102unsigned int bcm63xx_get_memory_size(void)
103{
104 return bcm63xx_memory_size;
105}
106
107static unsigned int detect_cpu_clock(void)
108{
109 switch (bcm63xx_get_cpu_id()) {
110 case BCM6328_CPU_ID:
111 {
112 unsigned int tmp, mips_pll_fcvo;
113
114 tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
115 mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
116 >> STRAPBUS_6328_FCVO_SHIFT;
117
118 switch (mips_pll_fcvo) {
119 case 0x12:
120 case 0x14:
121 case 0x19:
122 return 160000000;
123 case 0x1c:
124 return 192000000;
125 case 0x13:
126 case 0x15:
127 return 200000000;
128 case 0x1a:
129 return 384000000;
130 case 0x16:
131 return 400000000;
132 default:
133 return 320000000;
134 }
135
136 }
102 case BCM6338_CPU_ID:
103 /* BCM6338 has a fixed 240 Mhz frequency */
104 return 240000000;
105
106 case BCM6345_CPU_ID:
107 /* BCM6345 has a fixed 140Mhz frequency */
108 return 140000000;
109

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165/*
166 * attempt to detect the amount of memory installed
167 */
168static unsigned int detect_memory_size(void)
169{
170 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
171 u32 val;
172
137 case BCM6338_CPU_ID:
138 /* BCM6338 has a fixed 240 Mhz frequency */
139 return 240000000;
140
141 case BCM6345_CPU_ID:
142 /* BCM6345 has a fixed 140Mhz frequency */
143 return 140000000;
144

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200/*
201 * attempt to detect the amount of memory installed
202 */
203static unsigned int detect_memory_size(void)
204{
205 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
206 u32 val;
207
208 if (BCMCPU_IS_6328())
209 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
210
173 if (BCMCPU_IS_6345()) {
174 val = bcm_sdram_readl(SDRAM_MBASE_REG);
175 return (val * 8 * 1024 * 1024);
176 }
177
178 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
179 val = bcm_sdram_readl(SDRAM_CFG_REG);
180 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;

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232 expected_cpu_id = BCM6358_CPU_ID;
233 bcm63xx_regs_base = bcm6358_regs_base;
234 bcm63xx_irqs = bcm6358_irqs;
235 } else {
236 /* all newer chips have the same chip id location */
237 u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
238
239 switch (chip_id) {
211 if (BCMCPU_IS_6345()) {
212 val = bcm_sdram_readl(SDRAM_MBASE_REG);
213 return (val * 8 * 1024 * 1024);
214 }
215
216 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
217 val = bcm_sdram_readl(SDRAM_CFG_REG);
218 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;

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270 expected_cpu_id = BCM6358_CPU_ID;
271 bcm63xx_regs_base = bcm6358_regs_base;
272 bcm63xx_irqs = bcm6358_irqs;
273 } else {
274 /* all newer chips have the same chip id location */
275 u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
276
277 switch (chip_id) {
278 case BCM6328_CPU_ID:
279 expected_cpu_id = BCM6328_CPU_ID;
280 bcm63xx_regs_base = bcm6328_regs_base;
281 bcm63xx_irqs = bcm6328_irqs;
282 break;
240 case BCM6368_CPU_ID:
241 expected_cpu_id = BCM6368_CPU_ID;
242 bcm63xx_regs_base = bcm6368_regs_base;
243 bcm63xx_irqs = bcm6368_irqs;
244 break;
245 }
246 }
247 break;

--- 31 unchanged lines hidden --- 		283 case BCM6368_CPU_ID:
284 expected_cpu_id = BCM6368_CPU_ID;
285 bcm63xx_regs_base = bcm6368_regs_base;
286 bcm63xx_irqs = bcm6368_irqs;
287 break;
288 }
289 }
290 break;

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