cpu.c (13be798c57ebe5df09254832330f48c936ac39fd) cpu.c (2c8aaf71b0a4738ae8cb70d9367089bdb892aea3)
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */

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66 __GEN_CPU_REGS_TABLE(6358)
67};
68
69static const int bcm6358_irqs[] = {
70 __GEN_CPU_IRQ_TABLE(6358)
71
72};
73
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
7 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
8 */

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66 __GEN_CPU_REGS_TABLE(6358)
67};
68
69static const int bcm6358_irqs[] = {
70 __GEN_CPU_IRQ_TABLE(6358)
71
72};
73
74static const unsigned long bcm6362_regs_base[] = {
75 __GEN_CPU_REGS_TABLE(6362)
76};
77
78static const int bcm6362_irqs[] = {
79 __GEN_CPU_IRQ_TABLE(6362)
80
81};
82
74static const unsigned long bcm6368_regs_base[] = {
75 __GEN_CPU_REGS_TABLE(6368)
76};
77
78static const int bcm6368_irqs[] = {
79 __GEN_CPU_IRQ_TABLE(6368)
80
81};

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164 /* 16MHz * N1 * N2 / M1_CPU */
165 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
166 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
167 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
168 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
169 return (16 * 1000000 * n1 * n2) / m1;
170 }
171
83static const unsigned long bcm6368_regs_base[] = {
84 __GEN_CPU_REGS_TABLE(6368)
85};
86
87static const int bcm6368_irqs[] = {
88 __GEN_CPU_IRQ_TABLE(6368)
89
90};

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173 /* 16MHz * N1 * N2 / M1_CPU */
174 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
175 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
176 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
177 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
178 return (16 * 1000000 * n1 * n2) / m1;
179 }
180
181 case BCM6362_CPU_ID:
182 {
183 unsigned int tmp, mips_pll_fcvo;
184
185 tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
186 mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
187 >> STRAPBUS_6362_FCVO_SHIFT;
188 switch (mips_pll_fcvo) {
189 case 0x03:
190 case 0x0b:
191 case 0x13:
192 case 0x1b:
193 return 240000000;
194 case 0x04:
195 case 0x0c:
196 case 0x14:
197 case 0x1c:
198 return 160000000;
199 case 0x05:
200 case 0x0e:
201 case 0x16:
202 case 0x1e:
203 case 0x1f:
204 return 400000000;
205 case 0x06:
206 return 440000000;
207 case 0x07:
208 case 0x17:
209 return 384000000;
210 case 0x15:
211 case 0x1d:
212 return 200000000;
213 default:
214 return 320000000;
215 }
216 }
172 case BCM6368_CPU_ID:
173 {
174 unsigned int tmp, p1, p2, ndiv, m1;
175
176 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
177 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
178
179 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>

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200/*
201 * attempt to detect the amount of memory installed
202 */
203static unsigned int detect_memory_size(void)
204{
205 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
206 u32 val;
207
217 case BCM6368_CPU_ID:
218 {
219 unsigned int tmp, p1, p2, ndiv, m1;
220
221 /* (64MHz / P1) * P2 * NDIV / M1_CPU */
222 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
223
224 p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>

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245/*
246 * attempt to detect the amount of memory installed
247 */
248static unsigned int detect_memory_size(void)
249{
250 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
251 u32 val;
252
208 if (BCMCPU_IS_6328())
253 if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
209 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
210
211 if (BCMCPU_IS_6345()) {
212 val = bcm_sdram_readl(SDRAM_MBASE_REG);
213 return (val * 8 * 1024 * 1024);
214 }
215
216 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {

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292 case BCM6348_CPU_ID:
293 bcm63xx_regs_base = bcm6348_regs_base;
294 bcm63xx_irqs = bcm6348_irqs;
295 break;
296 case BCM6358_CPU_ID:
297 bcm63xx_regs_base = bcm6358_regs_base;
298 bcm63xx_irqs = bcm6358_irqs;
299 break;
254 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
255
256 if (BCMCPU_IS_6345()) {
257 val = bcm_sdram_readl(SDRAM_MBASE_REG);
258 return (val * 8 * 1024 * 1024);
259 }
260
261 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {

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337 case BCM6348_CPU_ID:
338 bcm63xx_regs_base = bcm6348_regs_base;
339 bcm63xx_irqs = bcm6348_irqs;
340 break;
341 case BCM6358_CPU_ID:
342 bcm63xx_regs_base = bcm6358_regs_base;
343 bcm63xx_irqs = bcm6358_irqs;
344 break;
345 case BCM6362_CPU_ID:
346 bcm63xx_regs_base = bcm6362_regs_base;
347 bcm63xx_irqs = bcm6362_irqs;
348 break;
300 case BCM6368_CPU_ID:
301 bcm63xx_regs_base = bcm6368_regs_base;
302 bcm63xx_irqs = bcm6368_irqs;
303 break;
304 default:
305 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
306 break;
307 }
308
309 bcm63xx_cpu_freq = detect_cpu_clock();
310 bcm63xx_memory_size = detect_memory_size();
311
312 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
313 bcm63xx_cpu_id, bcm63xx_cpu_rev);
314 printk(KERN_INFO "CPU frequency is %u MHz\n",
315 bcm63xx_cpu_freq / 1000000);
316 printk(KERN_INFO "%uMB of RAM installed\n",
317 bcm63xx_memory_size >> 20);
318}
349 case BCM6368_CPU_ID:
350 bcm63xx_regs_base = bcm6368_regs_base;
351 bcm63xx_irqs = bcm6368_irqs;
352 break;
353 default:
354 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
355 break;
356 }
357
358 bcm63xx_cpu_freq = detect_cpu_clock();
359 bcm63xx_memory_size = detect_memory_size();
360
361 printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
362 bcm63xx_cpu_id, bcm63xx_cpu_rev);
363 printk(KERN_INFO "CPU frequency is %u MHz\n",
364 bcm63xx_cpu_freq / 1000000);
365 printk(KERN_INFO "%uMB of RAM installed\n",
366 bcm63xx_memory_size >> 20);
367}