setup.c (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) setup.c (b83ba0b9df56f8404ccc6ebcc7050fb8294f0f20)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atheros AR71XX/AR724X/AR913X specific setup
4 *
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 *

--- 199 unchanged lines hidden (view full) ---

208
209unsigned int get_c0_compare_int(void)
210{
211 return CP0_LEGACY_COMPARE_IRQ;
212}
213
214void __init plat_mem_setup(void)
215{
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Atheros AR71XX/AR724X/AR913X specific setup
4 *
5 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
6 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
7 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
8 *

--- 199 unchanged lines hidden (view full) ---

208
209unsigned int get_c0_compare_int(void)
210{
211 return CP0_LEGACY_COMPARE_IRQ;
212}
213
214void __init plat_mem_setup(void)
215{
216 unsigned long fdt_start;
216 void *dtb;
217
218 set_io_port_base(KSEG1);
219
220 /* Get the position of the FDT passed by the bootloader */
217
218 set_io_port_base(KSEG1);
219
220 /* Get the position of the FDT passed by the bootloader */
221 fdt_start = fw_getenvl("fdt_start");
222 if (fdt_start)
223 __dt_setup_arch((void *)KSEG0ADDR(fdt_start));
224 else if (fw_passed_dtb)
225 __dt_setup_arch((void *)KSEG0ADDR(fw_passed_dtb));
221 dtb = (void *)fw_getenvl("fdt_start");
222 if (dtb == NULL)
223 dtb = get_fdt();
226
224
225 if (dtb)
226 __dt_setup_arch((void *)KSEG0ADDR(dtb));
227
227 ath79_reset_base = ioremap(AR71XX_RESET_BASE,
228 AR71XX_RESET_SIZE);
229 ath79_pll_base = ioremap(AR71XX_PLL_BASE,
230 AR71XX_PLL_SIZE);
231 ath79_detect_sys_type();
232 ath79_ddr_ctrl_init();
233
234 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);

--- 45 unchanged lines hidden --- 		228 ath79_reset_base = ioremap(AR71XX_RESET_BASE,
229 AR71XX_RESET_SIZE);
230 ath79_pll_base = ioremap(AR71XX_PLL_BASE,
231 AR71XX_PLL_SIZE);
232 ath79_detect_sys_type();
233 ath79_ddr_ctrl_init();
234
235 detect_memory_region(0, ATH79_MEM_SIZE_MIN, ATH79_MEM_SIZE_MAX);

--- 45 unchanged lines hidden ---