clock.c (e5451c8f8330e03ad3cfa16048b4daf961af434f) clock.c (c338d59d12dc93c3287160acd7e726b56dc94f43)
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *

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21
22#include <asm/div64.h>
23
24#include <asm/mach-ath79/ath79.h>
25#include <asm/mach-ath79/ar71xx_regs.h>
26#include "common.h"
27
28#define AR71XX_BASE_FREQ 40000000
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *

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21
22#include <asm/div64.h>
23
24#include <asm/mach-ath79/ath79.h>
25#include <asm/mach-ath79/ar71xx_regs.h>
26#include "common.h"
27
28#define AR71XX_BASE_FREQ 40000000
29#define AR724X_BASE_FREQ 5000000
29#define AR724X_BASE_FREQ 40000000
30#define AR913X_BASE_FREQ 5000000
31
32static struct clk *clks[3];
33static struct clk_onecell_data clk_data = {
34 .clks = clks,
35 .clk_num = ARRAY_SIZE(clks),
36};
37

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98 u32 div;
99
100 ref_rate = AR724X_BASE_FREQ;
101 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
102
103 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
104 freq = div * ref_rate;
105
30#define AR913X_BASE_FREQ 5000000
31
32static struct clk *clks[3];
33static struct clk_onecell_data clk_data = {
34 .clks = clks,
35 .clk_num = ARRAY_SIZE(clks),
36};
37

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98 u32 div;
99
100 ref_rate = AR724X_BASE_FREQ;
101 pll = ath79_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
102
103 div = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
104 freq = div * ref_rate;
105
106 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
107 freq *= div;
106 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
107 freq /= div;
108
109 cpu_rate = freq;
110
111 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
112 ddr_rate = freq / div;
113
114 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
115 ahb_rate = cpu_rate / div;

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109 cpu_rate = freq;
110
111 div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
112 ddr_rate = freq / div;
113
114 div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
115 ahb_rate = cpu_rate / div;

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