clock.c (65fc7f9957c52ad4fdf4ee5dfe3a75aa0a633d39) clock.c (97541ccfb9db2bb9cd1dde6344d5834438d14bda)
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19
1/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19
20#include <asm/div64.h>
21
20#include <asm/mach-ath79/ath79.h>
21#include <asm/mach-ath79/ar71xx_regs.h>
22#include "common.h"
23
24#define AR71XX_BASE_FREQ 40000000
25#define AR724X_BASE_FREQ 5000000
26#define AR913X_BASE_FREQ 5000000
27

--- 133 unchanged lines hidden (view full) ---

161 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
162 ath79_ahb_clk.rate = freq / t;
163 }
164
165 ath79_wdt_clk.rate = ath79_ref_clk.rate;
166 ath79_uart_clk.rate = ath79_ref_clk.rate;
167}
168
22#include <asm/mach-ath79/ath79.h>
23#include <asm/mach-ath79/ar71xx_regs.h>
24#include "common.h"
25
26#define AR71XX_BASE_FREQ 40000000
27#define AR724X_BASE_FREQ 5000000
28#define AR913X_BASE_FREQ 5000000
29

--- 133 unchanged lines hidden (view full) ---

163 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
164 ath79_ahb_clk.rate = freq / t;
165 }
166
167 ath79_wdt_clk.rate = ath79_ref_clk.rate;
168 ath79_uart_clk.rate = ath79_ref_clk.rate;
169}
170
171static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
172 u32 frac, u32 out_div)
173{
174 u64 t;
175 u32 ret;
176
177 t = ath79_ref_clk.rate;
178 t *= nint;
179 do_div(t, ref_div);
180 ret = t;
181
182 t = ath79_ref_clk.rate;
183 t *= nfrac;
184 do_div(t, ref_div * frac);
185 ret += t;
186
187 ret /= (1 << out_div);
188 return ret;
189}
190
169static void __init ar934x_clocks_init(void)
170{
191static void __init ar934x_clocks_init(void)
192{
171 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
193 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
172 u32 cpu_pll, ddr_pll;
173 u32 bootstrap;
194 u32 cpu_pll, ddr_pll;
195 u32 bootstrap;
196 void __iomem *dpll_base;
174
197
198 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
199
175 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
176 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
177 ath79_ref_clk.rate = 40 * 1000 * 1000;
178 else
179 ath79_ref_clk.rate = 25 * 1000 * 1000;
180
200 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
201 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
202 ath79_ref_clk.rate = 40 * 1000 * 1000;
203 else
204 ath79_ref_clk.rate = 25 * 1000 * 1000;
205
181 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
182 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
183 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
184 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
185 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
186 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
187 AR934X_PLL_CPU_CONFIG_NINT_MASK;
188 frac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
189 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
206 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
207 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
208 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
209 AR934X_SRIF_DPLL2_OUTDIV_MASK;
210 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
211 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
212 AR934X_SRIF_DPLL1_NINT_MASK;
213 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
214 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
215 AR934X_SRIF_DPLL1_REFDIV_MASK;
216 frac = 1 << 18;
217 } else {
218 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
219 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
220 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
221 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
222 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
223 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
224 AR934X_PLL_CPU_CONFIG_NINT_MASK;
225 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
226 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
227 frac = 1 << 6;
228 }
190
229
191 cpu_pll = nint * ath79_ref_clk.rate / ref_div;
192 cpu_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 6));
193 cpu_pll /= (1 << out_div);
230 cpu_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
231 nfrac, frac, out_div);
194
232
195 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
196 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
197 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
198 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
199 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
200 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
201 AR934X_PLL_DDR_CONFIG_NINT_MASK;
202 frac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
203 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
233 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
234 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
235 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
236 AR934X_SRIF_DPLL2_OUTDIV_MASK;
237 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
238 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
239 AR934X_SRIF_DPLL1_NINT_MASK;
240 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
241 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
242 AR934X_SRIF_DPLL1_REFDIV_MASK;
243 frac = 1 << 18;
244 } else {
245 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
246 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
247 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
248 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
249 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
250 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
251 AR934X_PLL_DDR_CONFIG_NINT_MASK;
252 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
253 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
254 frac = 1 << 10;
255 }
204
256
205 ddr_pll = nint * ath79_ref_clk.rate / ref_div;
206 ddr_pll += frac * ath79_ref_clk.rate / (ref_div * (1 << 10));
207 ddr_pll /= (1 << out_div);
257 ddr_pll = ar934x_get_pll_freq(ath79_ref_clk.rate, ref_div, nint,
258 nfrac, frac, out_div);
208
209 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
210
211 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
212 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
213
214 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
215 ath79_cpu_clk.rate = ath79_ref_clk.rate;

--- 19 unchanged lines hidden (view full) ---

235 ath79_ahb_clk.rate = ath79_ref_clk.rate;
236 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
237 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
238 else
239 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
240
241 ath79_wdt_clk.rate = ath79_ref_clk.rate;
242 ath79_uart_clk.rate = ath79_ref_clk.rate;
259
260 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
261
262 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
263 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
264
265 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
266 ath79_cpu_clk.rate = ath79_ref_clk.rate;

--- 19 unchanged lines hidden (view full) ---

286 ath79_ahb_clk.rate = ath79_ref_clk.rate;
287 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
288 ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
289 else
290 ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
291
292 ath79_wdt_clk.rate = ath79_ref_clk.rate;
293 ath79_uart_clk.rate = ath79_ref_clk.rate;
294
295 iounmap(dpll_base);
243}
244
245void __init ath79_clocks_init(void)
246{
247 if (soc_is_ar71xx())
248 ar71xx_clocks_init();
249 else if (soc_is_ar724x())
250 ar724x_clocks_init();

--- 69 unchanged lines hidden --- 		296}
297
298void __init ath79_clocks_init(void)
299{
300 if (soc_is_ar71xx())
301 ar71xx_clocks_init();
302 else if (soc_is_ar724x())
303 ar724x_clocks_init();

--- 69 unchanged lines hidden ---