dbdma.c (809f36c6f4a0568178c909ff1096ca83eae33f7d) dbdma.c (8b5690f8847490c1e3ea47266819833a13621253)
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC

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143 { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
144
145 { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
146
147 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149};
150
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * The Descriptor Based DMA channel manager that first appeared
5 * on the Au1550. I started with dma.c, but I think all that is
6 * left is this initial comment :-)
7 *
8 * Copyright 2004 Embedded Edge, LLC

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143 { AU1200_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
144
145 { AU1200_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
146
147 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
148 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
149};
150
151static dbdev_tab_t au1300_dbdev_tab[] __initdata = {
152 { AU1300_DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 },
153 { AU1300_DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 },
154 { AU1300_DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x10101004, 0, 0 },
155 { AU1300_DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 },
156 { AU1300_DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x10102004, 0, 0 },
157 { AU1300_DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 },
158 { AU1300_DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x10103004, 0, 0 },
159 { AU1300_DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 },
160
161 { AU1300_DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
162 { AU1300_DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
163 { AU1300_DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 },
164 { AU1300_DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 },
165
166 { AU1300_DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
167 { AU1300_DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
168
169 { AU1300_DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 },
170 { AU1300_DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 },
171 { AU1300_DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 },
172 { AU1300_DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 },
173 { AU1300_DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 },
174 { AU1300_DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 },
175 { AU1300_DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 },
176 { AU1300_DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 },
177
178 { AU1300_DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
179 { AU1300_DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
180
181 { AU1300_DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 },
182 { AU1300_DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 },
183
184 { AU1300_DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
185
186 { AU1300_DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 },
187
188 { AU1300_DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
189 { AU1300_DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
190
191 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
192 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
193};
194
195/* 32 predefined plus 32 custom */
196#define DBDEV_TAB_SIZE 64
197
198static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
199
200static dbdev_tab_t *find_dbdev_id(u32 id)
201{
202 int i;

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1058 for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
1059 dbdev_tab[ret].dev_id = ~0;
1060
1061 dbdma_gptr->ddma_config = 0;
1062 dbdma_gptr->ddma_throttle = 0;
1063 dbdma_gptr->ddma_inten = 0xffff;
1064 au_sync();
1065
151/* 32 predefined plus 32 custom */
152#define DBDEV_TAB_SIZE 64
153
154static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
155
156static dbdev_tab_t *find_dbdev_id(u32 id)
157{
158 int i;

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1014 for (ret = 32; ret < DBDEV_TAB_SIZE; ret++)
1015 dbdev_tab[ret].dev_id = ~0;
1016
1017 dbdma_gptr->ddma_config = 0;
1018 dbdma_gptr->ddma_throttle = 0;
1019 dbdma_gptr->ddma_inten = 0xffff;
1020 au_sync();
1021
1066 ret = request_irq(irq, dbdma_interrupt, IRQF_DISABLED, "dbdma",
1067 (void *)dbdma_gptr);
1022 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
1068 if (ret)
1069 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1070 else {
1071 dbdma_initialized = 1;
1072 register_syscore_ops(&alchemy_dbdma_syscore_ops);
1073 }
1074
1075 return ret;
1076}
1077
1078static int __init alchemy_dbdma_init(void)
1079{
1080 switch (alchemy_get_cputype()) {
1081 case ALCHEMY_CPU_AU1550:
1082 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1083 case ALCHEMY_CPU_AU1200:
1084 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1023 if (ret)
1024 printk(KERN_ERR "Cannot grab DBDMA interrupt!\n");
1025 else {
1026 dbdma_initialized = 1;
1027 register_syscore_ops(&alchemy_dbdma_syscore_ops);
1028 }
1029
1030 return ret;
1031}
1032
1033static int __init alchemy_dbdma_init(void)
1034{
1035 switch (alchemy_get_cputype()) {
1036 case ALCHEMY_CPU_AU1550:
1037 return dbdma_setup(AU1550_DDMA_INT, au1550_dbdev_tab);
1038 case ALCHEMY_CPU_AU1200:
1039 return dbdma_setup(AU1200_DDMA_INT, au1200_dbdev_tab);
1085 case ALCHEMY_CPU_AU1300:
1086 return dbdma_setup(AU1300_DDMA_INT, au1300_dbdev_tab);
1087 }
1088 return 0;
1089}
1090subsys_initcall(alchemy_dbdma_init);
1040 }
1041 return 0;
1042}
1043subsys_initcall(alchemy_dbdma_init);