m527xsim.h (b74b953b998bcc2db91b694446f3a2619ec32de6) m527xsim.h (7fc82b655a169039d8a58fde609b5e778573d5ab)
1/****************************************************************************/
2
3/*
4 * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m527xsim_h
11#define m527xsim_h
12/****************************************************************************/
13
1/****************************************************************************/
2
3/*
4 * m527xsim.h -- ColdFire 5270/5271 System Integration Module support.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 */
8
9/****************************************************************************/
10#ifndef m527xsim_h
11#define m527xsim_h
12/****************************************************************************/
13
14#define CPU_NAME "COLDFIRE(m527x)"
14
15
16
15/*
16 * Define the 5270/5271 SIM register set addresses.
17 */
18#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
19#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
20#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
21#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
22#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */

--- 237 unchanged lines hidden --- 		17/*
18 * Define the 5270/5271 SIM register set addresses.
19 */
20#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */
21#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 1 */
22#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
23#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
24#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */

--- 237 unchanged lines hidden ---