processor.h (9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) processor.h (bd3c5798484aa9a08302a844d7a75a2ee3b53d05)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5#ifndef _ASM_PROCESSOR_H
6#define _ASM_PROCESSOR_H
7
8#include <linux/atomic.h>

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75{ \
76 fpr->val##width[FPR_IDX(width, idx)] = val; \
77}
78
79BUILD_FPR_ACCESS(32)
80BUILD_FPR_ACCESS(64)
81
82struct loongarch_fpu {
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5#ifndef _ASM_PROCESSOR_H
6#define _ASM_PROCESSOR_H
7
8#include <linux/atomic.h>

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75{ \
76 fpr->val##width[FPR_IDX(width, idx)] = val; \
77}
78
79BUILD_FPR_ACCESS(32)
80BUILD_FPR_ACCESS(64)
81
82struct loongarch_fpu {
83 unsigned int fcsr;
84 uint64_t fcc; /* 8x8 */
83 uint64_t fcc; /* 8x8 */
84 uint32_t fcsr;
85 uint32_t ftop;
85 union fpureg fpr[NUM_FPU_REGS];
86};
87
86 union fpureg fpr[NUM_FPU_REGS];
87};
88
89struct loongarch_lbt {
90 /* Scratch registers */
91 unsigned long scr0;
92 unsigned long scr1;
93 unsigned long scr2;
94 unsigned long scr3;
95 /* Eflags register */
96 unsigned long eflags;
97};
98
88#define INIT_CPUMASK { \
89 {0,} \
90}
91
92#define ARCH_MIN_TASKALIGN 32
93
94struct loongarch_vdso_info;
95

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108
109 /* CSR registers */
110 unsigned long csr_prmd;
111 unsigned long csr_crmd;
112 unsigned long csr_euen;
113 unsigned long csr_ecfg;
114 unsigned long csr_badvaddr; /* Last user fault */
115
99#define INIT_CPUMASK { \
100 {0,} \
101}
102
103#define ARCH_MIN_TASKALIGN 32
104
105struct loongarch_vdso_info;
106

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119
120 /* CSR registers */
121 unsigned long csr_prmd;
122 unsigned long csr_crmd;
123 unsigned long csr_euen;
124 unsigned long csr_ecfg;
125 unsigned long csr_badvaddr; /* Last user fault */
126
116 /* Scratch registers */
117 unsigned long scr0;
118 unsigned long scr1;
119 unsigned long scr2;
120 unsigned long scr3;
121
122 /* Eflags register */
123 unsigned long eflags;
124
125 /* Other stuff associated with the thread. */
126 unsigned long trap_nr;
127 unsigned long error_code;
128 unsigned long single_step; /* Used by PTRACE_SINGLESTEP */
129 struct loongarch_vdso_info *vdso;
130
131 /*
132 * FPU & vector registers, must be at the last of inherited
133 * context because they are conditionally copied at fork().
134 */
135 struct loongarch_fpu fpu FPU_ALIGN;
127 /* Other stuff associated with the thread. */
128 unsigned long trap_nr;
129 unsigned long error_code;
130 unsigned long single_step; /* Used by PTRACE_SINGLESTEP */
131 struct loongarch_vdso_info *vdso;
132
133 /*
134 * FPU & vector registers, must be at the last of inherited
135 * context because they are conditionally copied at fork().
136 */
137 struct loongarch_fpu fpu FPU_ALIGN;
138 struct loongarch_lbt lbt; /* Also conditionally copied */
136
137 /* Hardware breakpoints pinned to this task. */
138 struct perf_event *hbp_break[LOONGARCH_MAX_BRP];
139 struct perf_event *hbp_watch[LOONGARCH_MAX_WRP];
140};
141
142#define thread_saved_ra(tsk) (tsk->thread.sched_ra)
143#define thread_saved_fp(tsk) (tsk->thread.sched_cfa)

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169 * Other stuff associated with the process \
170 */ \
171 .trap_nr = 0, \
172 .error_code = 0, \
173 /* \
174 * FPU & vector registers \
175 */ \
176 .fpu = { \
139
140 /* Hardware breakpoints pinned to this task. */
141 struct perf_event *hbp_break[LOONGARCH_MAX_BRP];
142 struct perf_event *hbp_watch[LOONGARCH_MAX_WRP];
143};
144
145#define thread_saved_ra(tsk) (tsk->thread.sched_ra)
146#define thread_saved_fp(tsk) (tsk->thread.sched_cfa)

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172 * Other stuff associated with the process \
173 */ \
174 .trap_nr = 0, \
175 .error_code = 0, \
176 /* \
177 * FPU & vector registers \
178 */ \
179 .fpu = { \
177 .fcsr = 0, \
178 .fcc = 0, \
180 .fcc = 0, \
181 .fcsr = 0, \
182 .ftop = 0, \
179 .fpr = {{{0,},},}, \
180 }, \
181 .hbp_break = {0}, \
182 .hbp_watch = {0}, \
183}
184
185struct task_struct;
186

--- 31 unchanged lines hidden --- 		183 .fpr = {{{0,},},}, \
184 }, \
185 .hbp_break = {0}, \
186 .hbp_watch = {0}, \
187}
188
189struct task_struct;
190

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