inst.h (446279168e030fd0ed68e2bba336bef8bb3da352) inst.h (49aef111e2dae176a7708b532118f33f24289248)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5#ifndef _ASM_INST_H
6#define _ASM_INST_H
7
8#include <linux/types.h>

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18
19#define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
20
21enum reg1i20_op {
22 lu12iw_op = 0x0a,
23 lu32id_op = 0x0b,
24};
25
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5#ifndef _ASM_INST_H
6#define _ASM_INST_H
7
8#include <linux/types.h>

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18
19#define ADDR_IMM(addr, INSN) ((addr & ADDR_IMMMASK_##INSN) >> ADDR_IMMSHIFT_##INSN)
20
21enum reg1i20_op {
22 lu12iw_op = 0x0a,
23 lu32id_op = 0x0b,
24};
25
26enum reg1i21_op {
27 beqz_op = 0x10,
28 bnez_op = 0x11,
29};
30
26enum reg2i12_op {
31enum reg2i12_op {
32 addiw_op = 0x0a,
33 addid_op = 0x0b,
27 lu52id_op = 0x0c,
34 lu52id_op = 0x0c,
35 ldb_op = 0xa0,
36 ldh_op = 0xa1,
37 ldw_op = 0xa2,
38 ldd_op = 0xa3,
39 stb_op = 0xa4,
40 sth_op = 0xa5,
41 stw_op = 0xa6,
42 std_op = 0xa7,
28};
29
30enum reg2i16_op {
31 jirl_op = 0x13,
43};
44
45enum reg2i16_op {
46 jirl_op = 0x13,
47 beq_op = 0x16,
48 bne_op = 0x17,
49 blt_op = 0x18,
50 bge_op = 0x19,
51 bltu_op = 0x1a,
52 bgeu_op = 0x1b,
32};
33
34struct reg0i26_format {
35 unsigned int immediate_h : 10;
36 unsigned int immediate_l : 16;
37 unsigned int opcode : 6;
38};
39

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105 LOONGARCH_GPR_S4,
106 LOONGARCH_GPR_S5,
107 LOONGARCH_GPR_S6,
108 LOONGARCH_GPR_S7,
109 LOONGARCH_GPR_S8,
110 LOONGARCH_GPR_MAX
111};
112
53};
54
55struct reg0i26_format {
56 unsigned int immediate_h : 10;
57 unsigned int immediate_l : 16;
58 unsigned int opcode : 6;
59};
60

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126 LOONGARCH_GPR_S4,
127 LOONGARCH_GPR_S5,
128 LOONGARCH_GPR_S6,
129 LOONGARCH_GPR_S7,
130 LOONGARCH_GPR_S8,
131 LOONGARCH_GPR_MAX
132};
133
134#define is_imm12_negative(val) is_imm_negative(val, 12)
135
136static inline bool is_imm_negative(unsigned long val, unsigned int bit)
137{
138 return val & (1UL << (bit - 1));
139}
140
141static inline bool is_branch_ins(union loongarch_instruction *ip)
142{
143 return ip->reg1i21_format.opcode >= beqz_op &&
144 ip->reg1i21_format.opcode <= bgeu_op;
145}
146
147static inline bool is_ra_save_ins(union loongarch_instruction *ip)
148{
149 /* st.d $ra, $sp, offset */
150 return ip->reg2i12_format.opcode == std_op &&
151 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
152 ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&
153 !is_imm12_negative(ip->reg2i12_format.immediate);
154}
155
156static inline bool is_stack_alloc_ins(union loongarch_instruction *ip)
157{
158 /* addi.d $sp, $sp, -imm */
159 return ip->reg2i12_format.opcode == addid_op &&
160 ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&
161 ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&
162 is_imm12_negative(ip->reg2i12_format.immediate);
163}
164
113u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
114u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
115u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest);
116
117#endif /* _ASM_INST_H */
165u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
166u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
167u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, unsigned long pc, unsigned long dest);
168
169#endif /* _ASM_INST_H */