| barrier.h (b7f8f259896f669f131713b0c74ba4d008daa71d) | barrier.h (0b1f557a1fa02174a982f557581e348d91987ec6) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2 3#ifndef __ASM_CSKY_BARRIER_H 4#define __ASM_CSKY_BARRIER_H 5 6#ifndef __ASSEMBLY__ 7 8#define nop() asm volatile ("nop\n":::"memory") --- 50 unchanged lines hidden (view full) --- 59#define ACQUIRE_FENCE ".long 0x8427c000\n" 60#define __smp_acquire_fence() __bar_brarw() 61#define __smp_release_fence() __bar_brwaw() 62 63#endif /* CONFIG_SMP */ 64 65/* 66 * sync: completion barrier, all sync.xx instructions | 1/* SPDX-License-Identifier: GPL-2.0 */ 2 3#ifndef __ASM_CSKY_BARRIER_H 4#define __ASM_CSKY_BARRIER_H 5 6#ifndef __ASSEMBLY__ 7 8#define nop() asm volatile ("nop\n":::"memory") --- 50 unchanged lines hidden (view full) --- 59#define ACQUIRE_FENCE ".long 0x8427c000\n" 60#define __smp_acquire_fence() __bar_brarw() 61#define __smp_release_fence() __bar_brwaw() 62 63#endif /* CONFIG_SMP */ 64 65/* 66 * sync: completion barrier, all sync.xx instructions |
| 67 * guarantee the last response recieved by bus transaction | 67 * guarantee the last response received by bus transaction |
| 68 * made by ld/st instructions before sync.s 69 * sync.s: inherit from sync, but also shareable to other cores 70 * sync.i: inherit from sync, but also flush cpu pipeline 71 * sync.is: the same with sync.i + sync.s 72 */ 73#define mb() asm volatile ("sync\n":::"memory") 74 75#ifdef CONFIG_CPU_HAS_CACHEV2 76/* 77 * Using three sync.is to prevent speculative PTW 78 */ 79#define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory") 80#endif 81 82#include <asm-generic/barrier.h> 83 84#endif /* __ASSEMBLY__ */ 85#endif /* __ASM_CSKY_BARRIER_H */ | 68 * made by ld/st instructions before sync.s 69 * sync.s: inherit from sync, but also shareable to other cores 70 * sync.i: inherit from sync, but also flush cpu pipeline 71 * sync.is: the same with sync.i + sync.s 72 */ 73#define mb() asm volatile ("sync\n":::"memory") 74 75#ifdef CONFIG_CPU_HAS_CACHEV2 76/* 77 * Using three sync.is to prevent speculative PTW 78 */ 79#define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory") 80#endif 81 82#include <asm-generic/barrier.h> 83 84#endif /* __ASSEMBLY__ */ 85#endif /* __ASM_CSKY_BARRIER_H */ |