| proc.S (9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) | proc.S (4df69e0df295822cdf816442fe4897f214cccb08) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Based on arch/arm/mm/proc.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * Copyright (C) 2012 ARM Ltd. 7 * Author: Catalin Marinas <catalin.marinas@arm.com> 8 */ --- 153 unchanged lines hidden (view full) --- 162alternative_else_nop_endif 163 164 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 165 isb 166 ret 167SYM_FUNC_END(cpu_do_resume) 168#endif 169 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Based on arch/arm/mm/proc.S 4 * 5 * Copyright (C) 2001 Deep Blue Solutions Ltd. 6 * Copyright (C) 2012 ARM Ltd. 7 * Author: Catalin Marinas <catalin.marinas@arm.com> 8 */ --- 153 unchanged lines hidden (view full) --- 162alternative_else_nop_endif 163 164 ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 165 isb 166 ret 167SYM_FUNC_END(cpu_do_resume) 168#endif 169 |
| 170 .pushsection ".idmap.text", "awx" | 170 .pushsection ".idmap.text", "a" |
| 171 172.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 173 adrp \tmp1, reserved_pg_dir 174 phys_to_ttbr \tmp2, \tmp1 175 offset_ttbr1 \tmp2, \tmp1 176 msr ttbr1_el1, \tmp2 177 isb 178 tlbi vmalle1 --- 17 unchanged lines hidden (view full) --- 196 ret 197SYM_FUNC_END(idmap_cpu_replace_ttbr1) 198 .popsection 199 200#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 201 202#define KPTI_NG_PTE_FLAGS (PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS) 203 | 171 172.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 173 adrp \tmp1, reserved_pg_dir 174 phys_to_ttbr \tmp2, \tmp1 175 offset_ttbr1 \tmp2, \tmp1 176 msr ttbr1_el1, \tmp2 177 isb 178 tlbi vmalle1 --- 17 unchanged lines hidden (view full) --- 196 ret 197SYM_FUNC_END(idmap_cpu_replace_ttbr1) 198 .popsection 199 200#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 201 202#define KPTI_NG_PTE_FLAGS (PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS) 203 |
| 204 .pushsection ".idmap.text", "awx" | 204 .pushsection ".idmap.text", "a" |
| 205 206 .macro kpti_mk_tbl_ng, type, num_entries 207 add end_\type\()p, cur_\type\()p, #\num_entries * 8 208.Ldo_\type: 209 ldr \type, [cur_\type\()p] // Load the entry 210 tbz \type, #0, .Lnext_\type // Skip invalid and 211 tbnz \type, #11, .Lnext_\type // non-global entries 212 orr \type, \type, #PTE_NG // Same bit for blocks and pages --- 182 unchanged lines hidden (view full) --- 395 * 396 * Initialise the processor for turning the MMU on. 397 * 398 * Input: 399 * x0 - actual number of VA bits (ignored unless VA_BITS > 48) 400 * Output: 401 * Return in x0 the value of the SCTLR_EL1 register. 402 */ | 205 206 .macro kpti_mk_tbl_ng, type, num_entries 207 add end_\type\()p, cur_\type\()p, #\num_entries * 8 208.Ldo_\type: 209 ldr \type, [cur_\type\()p] // Load the entry 210 tbz \type, #0, .Lnext_\type // Skip invalid and 211 tbnz \type, #11, .Lnext_\type // non-global entries 212 orr \type, \type, #PTE_NG // Same bit for blocks and pages --- 182 unchanged lines hidden (view full) --- 395 * 396 * Initialise the processor for turning the MMU on. 397 * 398 * Input: 399 * x0 - actual number of VA bits (ignored unless VA_BITS > 48) 400 * Output: 401 * Return in x0 the value of the SCTLR_EL1 register. 402 */ |
| 403 .pushsection ".idmap.text", "awx" | 403 .pushsection ".idmap.text", "a" |
| 404SYM_FUNC_START(__cpu_setup) 405 tlbi vmalle1 // Invalidate local TLB 406 dsb nsh 407 408 mov x1, #3 << 20 409 msr cpacr_el1, x1 // Enable FP/ASIMD 410 mov x1, #1 << 12 // Reset mdscr_el1 and disable 411 msr mdscr_el1, x1 // access to the DCC from EL0 --- 54 unchanged lines hidden --- | 404SYM_FUNC_START(__cpu_setup) 405 tlbi vmalle1 // Invalidate local TLB 406 dsb nsh 407 408 mov x1, #3 << 20 409 msr cpacr_el1, x1 // Enable FP/ASIMD 410 mov x1, #1 << 12 // Reset mdscr_el1 and disable 411 msr mdscr_el1, x1 // access to the DCC from EL0 --- 54 unchanged lines hidden --- |