cache.S (4ba24fef3eb3b142197135223b90ced2f319cd53) cache.S (68234df4ea7939f98431aa81113fbdce10c4a84b)
1/*
2 * Cache maintenance
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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22#include <linux/init.h>
23#include <asm/assembler.h>
24#include <asm/cpufeature.h>
25#include <asm/alternative-asm.h>
26
27#include "proc-macros.S"
28
29/*
1/*
2 * Cache maintenance
3 *
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as

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22#include <linux/init.h>
23#include <asm/assembler.h>
24#include <asm/cpufeature.h>
25#include <asm/alternative-asm.h>
26
27#include "proc-macros.S"
28
29/*
30 * __flush_dcache_all()
31 *
32 * Flush the whole D-cache.
33 *
34 * Corrupted registers: x0-x7, x9-x11
35 */
36__flush_dcache_all:
37 dmb sy // ensure ordering with previous memory accesses
38 mrs x0, clidr_el1 // read clidr
39 and x3, x0, #0x7000000 // extract loc from clidr
40 lsr x3, x3, #23 // left align loc bit field
41 cbz x3, finished // if loc is 0, then no need to clean
42 mov x10, #0 // start clean at cache level 0
43loop1:
44 add x2, x10, x10, lsr #1 // work out 3x current cache level
45 lsr x1, x0, x2 // extract cache type bits from clidr
46 and x1, x1, #7 // mask of the bits for current cache only
47 cmp x1, #2 // see what cache we have at this level
48 b.lt skip // skip if no cache, or just i-cache
49 save_and_disable_irqs x9 // make CSSELR and CCSIDR access atomic
50 msr csselr_el1, x10 // select current cache level in csselr
51 isb // isb to sych the new cssr&csidr
52 mrs x1, ccsidr_el1 // read the new ccsidr
53 restore_irqs x9
54 and x2, x1, #7 // extract the length of the cache lines
55 add x2, x2, #4 // add 4 (line length offset)
56 mov x4, #0x3ff
57 and x4, x4, x1, lsr #3 // find maximum number on the way size
58 clz w5, w4 // find bit position of way size increment
59 mov x7, #0x7fff
60 and x7, x7, x1, lsr #13 // extract max number of the index size
61loop2:
62 mov x9, x4 // create working copy of max way size
63loop3:
64 lsl x6, x9, x5
65 orr x11, x10, x6 // factor way and cache number into x11
66 lsl x6, x7, x2
67 orr x11, x11, x6 // factor index number into x11
68 dc cisw, x11 // clean & invalidate by set/way
69 subs x9, x9, #1 // decrement the way
70 b.ge loop3
71 subs x7, x7, #1 // decrement the index
72 b.ge loop2
73skip:
74 add x10, x10, #2 // increment cache number
75 cmp x3, x10
76 b.gt loop1
77finished:
78 mov x10, #0 // swith back to cache level 0
79 msr csselr_el1, x10 // select current cache level in csselr
80 dsb sy
81 isb
82 ret
83ENDPROC(__flush_dcache_all)
84
85/*
86 * flush_cache_all()
87 *
88 * Flush the entire cache system. The data cache flush is now achieved
89 * using atomic clean / invalidates working outwards from L1 cache. This
90 * is done using Set/Way based cache maintainance instructions. The
91 * instruction cache can still be invalidated back to the point of
92 * unification in a single instruction.
93 */
94ENTRY(flush_cache_all)
95 mov x12, lr
96 bl __flush_dcache_all
97 mov x0, #0
98 ic ialluis // I+BTB cache invalidate
99 ret x12
100ENDPROC(flush_cache_all)
101
102/*
103 * flush_icache_range(start,end)
104 *
105 * Ensure that the I and D caches are coherent within specified region.
106 * This is typically used when code has been written to a memory region,
107 * and will be executed.
108 *
109 * - start - virtual start address of region
110 * - end - virtual end address of region

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30 * flush_icache_range(start,end)
31 *
32 * Ensure that the I and D caches are coherent within specified region.
33 * This is typically used when code has been written to a memory region,
34 * and will be executed.
35 *
36 * - start - virtual start address of region
37 * - end - virtual end address of region

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