switch.c (77b679453d3364688ff3e5153c0be5b2b52672b7) switch.c (e5ecedcd7cc231a115c11cfed79635583ef4f882)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <hyp/switch.h>
8

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72 /*
73 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
74 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
75 * except for some missing controls, such as TAM.
76 * In this case, CPTR_EL2.TAM has the same position with or without
77 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
78 * shift value for trapping the AMU accesses.
79 */
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#include <hyp/switch.h>
8

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72 /*
73 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
74 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
75 * except for some missing controls, such as TAM.
76 * In this case, CPTR_EL2.TAM has the same position with or without
77 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
78 * shift value for trapping the AMU accesses.
79 */
80 u64 val = CPACR_ELx_TTA | CPTR_EL2_TAM;
80 u64 val = CPACR_EL1_TTA | CPTR_EL2_TAM;
81
82 if (guest_owns_fp_regs()) {
81
82 if (guest_owns_fp_regs()) {
83 val |= CPACR_ELx_FPEN;
83 val |= CPACR_EL1_FPEN;
84 if (vcpu_has_sve(vcpu))
84 if (vcpu_has_sve(vcpu))
85 val |= CPACR_ELx_ZEN;
85 val |= CPACR_EL1_ZEN;
86 } else {
87 __activate_traps_fpsimd32(vcpu);
88 }
89
90 if (!vcpu_has_nv(vcpu))
91 goto write;
92
93 /*

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117 * - CPTR_EL2.xEN = x0, traps are enabled
118 * - CPTR_EL2.xEN = x1, traps are disabled
119 *
120 * In other words, bit[0] determines if guest accesses trap or not. In
121 * the interest of simplicity, clear the entire field if the guest
122 * hypervisor has traps enabled to dispel any illusion of something more
123 * complicated taking place.
124 */
86 } else {
87 __activate_traps_fpsimd32(vcpu);
88 }
89
90 if (!vcpu_has_nv(vcpu))
91 goto write;
92
93 /*

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117 * - CPTR_EL2.xEN = x0, traps are enabled
118 * - CPTR_EL2.xEN = x1, traps are disabled
119 *
120 * In other words, bit[0] determines if guest accesses trap or not. In
121 * the interest of simplicity, clear the entire field if the guest
122 * hypervisor has traps enabled to dispel any illusion of something more
123 * complicated taking place.
124 */
125 if (!(SYS_FIELD_GET(CPACR_ELx, FPEN, cptr) & BIT(0)))
126 val &= ~CPACR_ELx_FPEN;
127 if (!(SYS_FIELD_GET(CPACR_ELx, ZEN, cptr) & BIT(0)))
128 val &= ~CPACR_ELx_ZEN;
125 if (!(SYS_FIELD_GET(CPACR_EL1, FPEN, cptr) & BIT(0)))
126 val &= ~CPACR_EL1_FPEN;
127 if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
128 val &= ~CPACR_EL1_ZEN;
129
130 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
129
130 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
131 val |= cptr & CPACR_ELx_E0POE;
131 val |= cptr & CPACR_EL1_E0POE;
132
133 val |= cptr & CPTR_EL2_TCPAC;
134
135write:
136 write_sysreg(val, cpacr_el1);
137}
138
139static void __activate_traps(struct kvm_vcpu *vcpu)

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133 val |= cptr & CPTR_EL2_TCPAC;
134
135write:
136 write_sysreg(val, cpacr_el1);
137}
138
139static void __activate_traps(struct kvm_vcpu *vcpu)

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