pkvm.c (38e961097e04e7adfe1d3335e3371e97c1723064) pkvm.c (e5ecedcd7cc231a115c11cfed79635583ef4f882)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2021 Google LLC
4 * Author: Fuad Tabba <tabba@google.com>
5 */
6
7#include <linux/kvm_host.h>
8#include <linux/mm.h>

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63 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) {
64 hcr_clear |= HCR_AMVOFFEN;
65 cptr_set |= CPTR_EL2_TAM;
66 }
67
68 /* Trap SVE */
69 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) {
70 if (has_hvhe())
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2021 Google LLC
4 * Author: Fuad Tabba <tabba@google.com>
5 */
6
7#include <linux/kvm_host.h>
8#include <linux/mm.h>

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63 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_AMU), feature_ids)) {
64 hcr_clear |= HCR_AMVOFFEN;
65 cptr_set |= CPTR_EL2_TAM;
66 }
67
68 /* Trap SVE */
69 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_SVE), feature_ids)) {
70 if (has_hvhe())
71 cptr_clear |= CPACR_ELx_ZEN;
71 cptr_clear |= CPACR_EL1_ZEN;
72 else
73 cptr_set |= CPTR_EL2_TZ;
74 }
75
76 vcpu->arch.hcr_el2 |= hcr_set;
77 vcpu->arch.hcr_el2 &= ~hcr_clear;
78 vcpu->arch.cptr_el2 |= cptr_set;
79 vcpu->arch.cptr_el2 &= ~cptr_clear;

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121
122 /* Trap OS Double Lock */
123 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DoubleLock), feature_ids))
124 mdcr_set |= MDCR_EL2_TDOSA;
125
126 /* Trap SPE */
127 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) {
128 mdcr_set |= MDCR_EL2_TPMS;
72 else
73 cptr_set |= CPTR_EL2_TZ;
74 }
75
76 vcpu->arch.hcr_el2 |= hcr_set;
77 vcpu->arch.hcr_el2 &= ~hcr_clear;
78 vcpu->arch.cptr_el2 |= cptr_set;
79 vcpu->arch.cptr_el2 &= ~cptr_clear;

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121
122 /* Trap OS Double Lock */
123 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_DoubleLock), feature_ids))
124 mdcr_set |= MDCR_EL2_TDOSA;
125
126 /* Trap SPE */
127 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMSVer), feature_ids)) {
128 mdcr_set |= MDCR_EL2_TPMS;
129 mdcr_clear |= MDCR_EL2_E2PB_MASK;
129 mdcr_clear |= MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT;
130 }
131
132 /* Trap Trace Filter */
133 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids))
134 mdcr_set |= MDCR_EL2_TTRF;
135
136 /* Trap Trace */
137 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) {
138 if (has_hvhe())
139 cptr_set |= CPACR_EL1_TTA;
140 else
141 cptr_set |= CPTR_EL2_TTA;
142 }
143
144 /* Trap External Trace */
145 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids))
130 }
131
132 /* Trap Trace Filter */
133 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceFilt), feature_ids))
134 mdcr_set |= MDCR_EL2_TTRF;
135
136 /* Trap Trace */
137 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_TraceVer), feature_ids)) {
138 if (has_hvhe())
139 cptr_set |= CPACR_EL1_TTA;
140 else
141 cptr_set |= CPTR_EL2_TTA;
142 }
143
144 /* Trap External Trace */
145 if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_ExtTrcBuff), feature_ids))
146 mdcr_clear |= MDCR_EL2_E2TB_MASK;
146 mdcr_clear |= MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT;
147
148 vcpu->arch.mdcr_el2 |= mdcr_set;
149 vcpu->arch.mdcr_el2 &= ~mdcr_clear;
150 vcpu->arch.cptr_el2 |= cptr_set;
151}
152
153/*
154 * Set trap register values based on features in ID_AA64MMFR0.

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148 vcpu->arch.mdcr_el2 |= mdcr_set;
149 vcpu->arch.mdcr_el2 &= ~mdcr_clear;
150 vcpu->arch.cptr_el2 |= cptr_set;
151}
152
153/*
154 * Set trap register values based on features in ID_AA64MMFR0.

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