process.c (1758047057dbe329be712a31b79db7151b5871f8) process.c (38e0257e0e6f4fef2aa2966b089b56a8b1cfb75c)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Based on arch/arm/kernel/process.c
4 *
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
8 */

--- 425 unchanged lines hidden (view full) ---

434
435static void entry_task_switch(struct task_struct *next)
436{
437 __this_cpu_write(__entry_task, next);
438}
439
440/*
441 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Based on arch/arm/kernel/process.c
4 *
5 * Original Copyright (C) 1995 Linus Torvalds
6 * Copyright (C) 1996-2000 Russell King - Converted to ARM.
7 * Copyright (C) 2012 ARM Ltd.
8 */

--- 425 unchanged lines hidden (view full) ---

434
435static void entry_task_switch(struct task_struct *next)
436{
437 __this_cpu_write(__entry_task, next);
438}
439
440/*
441 * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT.
442 * Assuming the virtual counter is enabled at the beginning of times:
443 *
444 * - disable access when switching from a 64bit task to a 32bit task
445 * - enable access when switching from a 32bit task to a 64bit task
442 * Ensure access is disabled when switching to a 32bit task, ensure
443 * access is enabled when switching to a 64bit task.
446 */
444 */
447static void erratum_1418040_thread_switch(struct task_struct *prev,
448 struct task_struct *next)
445static void erratum_1418040_thread_switch(struct task_struct *next)
449{
446{
450 bool prev32, next32;
451 u64 val;
452
453 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040))
447 if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) ||
448 !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
454 return;
455
449 return;
450
456 prev32 = is_compat_thread(task_thread_info(prev));
457 next32 = is_compat_thread(task_thread_info(next));
458
459 if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040))
460 return;
461
462 val = read_sysreg(cntkctl_el1);
463
464 if (!next32)
465 val |= ARCH_TIMER_USR_VCT_ACCESS_EN;
451 if (is_compat_thread(task_thread_info(next)))
452 sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0);
466 else
453 else
467 val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN;
454 sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN);
455}
468
456
469 write_sysreg(val, cntkctl_el1);
457static void erratum_1418040_new_exec(void)
458{
459 preempt_disable();
460 erratum_1418040_thread_switch(current);
461 preempt_enable();
470}
471
472/*
473 * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
474 * this function must be called with preemption disabled and the update to
475 * sctlr_user must be made in the same preemption disabled block so that
476 * __switch_to() does not see the variable update before the SCTLR_EL1 one.
477 */

--- 18 unchanged lines hidden (view full) ---

496 struct task_struct *last;
497
498 fpsimd_thread_switch(next);
499 tls_thread_switch(next);
500 hw_breakpoint_thread_switch(next);
501 contextidr_thread_switch(next);
502 entry_task_switch(next);
503 ssbs_thread_switch(next);
462}
463
464/*
465 * __switch_to() checks current->thread.sctlr_user as an optimisation. Therefore
466 * this function must be called with preemption disabled and the update to
467 * sctlr_user must be made in the same preemption disabled block so that
468 * __switch_to() does not see the variable update before the SCTLR_EL1 one.
469 */

--- 18 unchanged lines hidden (view full) ---

488 struct task_struct *last;
489
490 fpsimd_thread_switch(next);
491 tls_thread_switch(next);
492 hw_breakpoint_thread_switch(next);
493 contextidr_thread_switch(next);
494 entry_task_switch(next);
495 ssbs_thread_switch(next);
504 erratum_1418040_thread_switch(prev, next);
496 erratum_1418040_thread_switch(next);
505 ptrauth_thread_switch_user(next);
506
507 /*
508 * Complete any pending TLB or cache maintenance on this CPU in case
509 * the thread migrates to a different CPU.
510 * This full barrier is also required by the membarrier system
511 * call.
512 */

--- 93 unchanged lines hidden (view full) ---

606 force_compatible_cpus_allowed_ptr(current);
607 } else if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) {
608 relax_compatible_cpus_allowed_ptr(current);
609 }
610
611 current->mm->context.flags = mmflags;
612 ptrauth_thread_init_user();
613 mte_thread_init_user();
497 ptrauth_thread_switch_user(next);
498
499 /*
500 * Complete any pending TLB or cache maintenance on this CPU in case
501 * the thread migrates to a different CPU.
502 * This full barrier is also required by the membarrier system
503 * call.
504 */

--- 93 unchanged lines hidden (view full) ---

598 force_compatible_cpus_allowed_ptr(current);
599 } else if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) {
600 relax_compatible_cpus_allowed_ptr(current);
601 }
602
603 current->mm->context.flags = mmflags;
604 ptrauth_thread_init_user();
605 mte_thread_init_user();
606 erratum_1418040_new_exec();
614
615 if (task_spec_ssb_noexec(current)) {
616 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
617 PR_SPEC_ENABLE);
618 }
619}
620
621#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI

--- 100 unchanged lines hidden --- 		607
608 if (task_spec_ssb_noexec(current)) {
609 arch_prctl_spec_ctrl_set(current, PR_SPEC_STORE_BYPASS,
610 PR_SPEC_ENABLE);
611 }
612}
613
614#ifdef CONFIG_ARM64_TAGGED_ADDR_ABI

--- 100 unchanged lines hidden ---