| head.S (652af899799354049b273af897b798b8f03fdd88) | head.S (828e9834e9a5b7e61046aa3c5f603a4fecba2fb4) |
|---|---|
| 1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> --- 109 unchanged lines hidden (view full) --- 118 .byte 0x41 // Magic number, "ARM\x64" 119 .byte 0x52 120 .byte 0x4d 121 .byte 0x64 122 .word 0 // reserved 123 124ENTRY(stext) 125 mov x21, x0 // x21=FDT | 1/* 2 * Low-level CPU initialisation 3 * Based on arch/arm/kernel/head.S 4 * 5 * Copyright (C) 1994-2002 Russell King 6 * Copyright (C) 2003-2012 ARM Ltd. 7 * Authors: Catalin Marinas <catalin.marinas@arm.com> 8 * Will Deacon <will.deacon@arm.com> --- 109 unchanged lines hidden (view full) --- 118 .byte 0x41 // Magic number, "ARM\x64" 119 .byte 0x52 120 .byte 0x4d 121 .byte 0x64 122 .word 0 // reserved 123 124ENTRY(stext) 125 mov x21, x0 // x21=FDT |
| 126 bl el2_setup // Drop to EL1, w20=cpu_boot_mode |
|
| 126 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET | 127 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET |
| 127 bl el2_setup // Drop to EL1 | 128 bl set_cpu_boot_mode_flag |
| 128 mrs x22, midr_el1 // x22=cpuid 129 mov x0, x22 130 bl lookup_processor_type 131 mov x23, x0 // x23=current cpu_table 132 cbz x23, __error_p // invalid processor (x23=0)? 133 bl __vet_fdt 134 bl __create_page_tables // x25=TTBR0, x26=TTBR1 135 /* --- 9 unchanged lines hidden (view full) --- 145 ldr x12, [x23, #CPU_INFO_SETUP] 146 add x12, x12, x28 // __virt_to_phys 147 br x12 // initialise processor 148ENDPROC(stext) 149 150/* 151 * If we're fortunate enough to boot at EL2, ensure that the world is 152 * sane before dropping to EL1. | 129 mrs x22, midr_el1 // x22=cpuid 130 mov x0, x22 131 bl lookup_processor_type 132 mov x23, x0 // x23=current cpu_table 133 cbz x23, __error_p // invalid processor (x23=0)? 134 bl __vet_fdt 135 bl __create_page_tables // x25=TTBR0, x26=TTBR1 136 /* --- 9 unchanged lines hidden (view full) --- 146 ldr x12, [x23, #CPU_INFO_SETUP] 147 add x12, x12, x28 // __virt_to_phys 148 br x12 // initialise processor 149ENDPROC(stext) 150 151/* 152 * If we're fortunate enough to boot at EL2, ensure that the world is 153 * sane before dropping to EL1. |
| 154 * 155 * Returns either BOOT_CPU_MODE_EL1 or BOOT_CPU_MODE_EL2 in x20 if 156 * booted in EL1 or EL2 respectively. |
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| 153 */ 154ENTRY(el2_setup) 155 mrs x0, CurrentEL 156 cmp x0, #PSR_MODE_EL2t 157 ccmp x0, #PSR_MODE_EL2h, #0x4, ne | 157 */ 158ENTRY(el2_setup) 159 mrs x0, CurrentEL 160 cmp x0, #PSR_MODE_EL2t 161 ccmp x0, #PSR_MODE_EL2h, #0x4, ne |
| 158 ldr x0, =__boot_cpu_mode // Compute __boot_cpu_mode 159 add x0, x0, x28 | |
| 160 b.eq 1f | 162 b.eq 1f |
| 161 str wzr, [x0] // Remember we don't have EL2... | 163 mov w20, #BOOT_CPU_MODE_EL1 // This cpu booted in EL1 |
| 162 ret 163 164 /* Hyp configuration. */ | 164 ret 165 166 /* Hyp configuration. */ |
| 1651: ldr w1, =BOOT_CPU_MODE_EL2 166 str w1, [x0, #4] // This CPU has EL2 167 mov x0, #(1 << 31) // 64-bit EL1 | 1671: mov x0, #(1 << 31) // 64-bit EL1 |
| 168 msr hcr_el2, x0 169 170 /* Generic timers. */ 171 mrs x0, cnthctl_el2 172 orr x0, x0, #3 // Enable EL1 physical timers 173 msr cnthctl_el2, x0 174 msr cntvoff_el2, xzr // Clear virtual offset 175 --- 23 unchanged lines hidden (view full) --- 199 adr x0, __hyp_stub_vectors 200 msr vbar_el2, x0 201 202 /* spsr */ 203 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 204 PSR_MODE_EL1h) 205 msr spsr_el2, x0 206 msr elr_el2, lr | 168 msr hcr_el2, x0 169 170 /* Generic timers. */ 171 mrs x0, cnthctl_el2 172 orr x0, x0, #3 // Enable EL1 physical timers 173 msr cnthctl_el2, x0 174 msr cntvoff_el2, xzr // Clear virtual offset 175 --- 23 unchanged lines hidden (view full) --- 199 adr x0, __hyp_stub_vectors 200 msr vbar_el2, x0 201 202 /* spsr */ 203 mov x0, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\ 204 PSR_MODE_EL1h) 205 msr spsr_el2, x0 206 msr elr_el2, lr |
| 207 mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2 |
|
| 207 eret 208ENDPROC(el2_setup) 209 210/* | 208 eret 209ENDPROC(el2_setup) 210 211/* |
| 212 * Sets the __boot_cpu_mode flag depending on the CPU boot mode passed 213 * in x20. See arch/arm64/include/asm/virt.h for more info. 214 */ 215ENTRY(set_cpu_boot_mode_flag) 216 ldr x1, =__boot_cpu_mode // Compute __boot_cpu_mode 217 add x1, x1, x28 218 cmp w20, #BOOT_CPU_MODE_EL2 219 b.ne 1f 220 add x1, x1, #4 2211: str w20, [x1] // This CPU has booted in EL1 222 ret 223ENDPROC(set_cpu_boot_mode_flag) 224 225/* |
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| 211 * We need to find out the CPU boot mode long after boot, so we need to 212 * store it in a writable variable. 213 * 214 * This is not in .bss, because we set it sufficiently early that the boot-time 215 * zeroing of .bss would clobber it. 216 */ 217 .pushsection .data 218ENTRY(__boot_cpu_mode) --- 10 unchanged lines hidden (view full) --- 2291: .quad . 230 .quad secondary_holding_pen_release 231 232 /* 233 * This provides a "holding pen" for platforms to hold all secondary 234 * cores are held until we're ready for them to initialise. 235 */ 236ENTRY(secondary_holding_pen) | 226 * We need to find out the CPU boot mode long after boot, so we need to 227 * store it in a writable variable. 228 * 229 * This is not in .bss, because we set it sufficiently early that the boot-time 230 * zeroing of .bss would clobber it. 231 */ 232 .pushsection .data 233ENTRY(__boot_cpu_mode) --- 10 unchanged lines hidden (view full) --- 2441: .quad . 245 .quad secondary_holding_pen_release 246 247 /* 248 * This provides a "holding pen" for platforms to hold all secondary 249 * cores are held until we're ready for them to initialise. 250 */ 251ENTRY(secondary_holding_pen) |
| 237 bl __calc_phys_offset // x24=phys offset 238 bl el2_setup // Drop to EL1 | 252 bl el2_setup // Drop to EL1, w20=cpu_boot_mode 253 bl __calc_phys_offset // x24=PHYS_OFFSET, x28=PHYS_OFFSET-PAGE_OFFSET 254 bl set_cpu_boot_mode_flag |
| 239 mrs x0, mpidr_el1 240 ldr x1, =MPIDR_HWID_BITMASK 241 and x0, x0, x1 242 adr x1, 1b 243 ldp x2, x3, [x1] 244 sub x1, x1, x2 245 add x3, x3, x1 246pen: ldr x4, [x3] --- 317 unchanged lines hidden --- | 255 mrs x0, mpidr_el1 256 ldr x1, =MPIDR_HWID_BITMASK 257 and x0, x0, x1 258 adr x1, 1b 259 ldp x2, x3, [x1] 260 sub x1, x1, x2 261 add x3, x3, x1 262pen: ldr x4, [x3] --- 317 unchanged lines hidden --- |