entry-fpsimd.S (c9f6890bca111a879a8af1f2390ac49cf05b11df) entry-fpsimd.S (ad4711f962e08eff8d6e9b03f9670b1af6ea9395)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * FP/SIMD state saving and restoring
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8

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64 */
65SYM_FUNC_START(sve_load_from_fpsimd_state)
66 sve_load_vq x1, x2, x3
67 fpsimd_restore x0, 8
68 sve_flush_p_ffr
69 ret
70SYM_FUNC_END(sve_load_from_fpsimd_state)
71
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * FP/SIMD state saving and restoring
4 *
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8

--- 55 unchanged lines hidden (view full) ---

64 */
65SYM_FUNC_START(sve_load_from_fpsimd_state)
66 sve_load_vq x1, x2, x3
67 fpsimd_restore x0, 8
68 sve_flush_p_ffr
69 ret
70SYM_FUNC_END(sve_load_from_fpsimd_state)
71
72/* Zero all SVE registers but the first 128-bits of each vector */
72/*
73 * Zero all SVE registers but the first 128-bits of each vector
74 *
75 * VQ must already be configured by caller, any further updates of VQ
76 * will need to ensure that the register state remains valid.
77 *
78 * x0 = VQ - 1
79 */
73SYM_FUNC_START(sve_flush_live)
80SYM_FUNC_START(sve_flush_live)
81 cbz x0, 1f // A VQ-1 of 0 is 128 bits so no extra Z state
74 sve_flush_z
82 sve_flush_z
75 sve_flush_p_ffr
831: sve_flush_p_ffr
76 ret
77SYM_FUNC_END(sve_flush_live)
78
79#endif /* CONFIG_ARM64_SVE */
84 ret
85SYM_FUNC_END(sve_flush_live)
86
87#endif /* CONFIG_ARM64_SVE */