cpufeature.c (988699f9e6b61d25a1448f7ff3c4a80b41e9d9e6) cpufeature.c (bf49e73dde7dd54bb52e67e0a1b72e748a04d0b4)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because

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495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
496 ARM64_FTR_END,
497};
498
499static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
500 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),
501 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Contains CPU feature definitions
4 *
5 * Copyright (C) 2015 ARM Ltd.
6 *
7 * A note for the weary kernel hacker: the code here is confusing and hard to
8 * follow! That's partly because it's solving a nasty problem, but also because

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495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0),
496 ARM64_FTR_END,
497};
498
499static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = {
500 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE),
501 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0),
502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0),
503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
504 ARM64_FTR_END,
505};
506
507static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {
508 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0),
509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0),
510 ARM64_FTR_END,

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2291}
2292#endif /* CONFIG_ARM64_E0PD */
2293
2294#ifdef CONFIG_ARM64_PSEUDO_NMI
2295static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2296 int scope)
2297{
2298 /*
504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0),
505 ARM64_FTR_END,
506};
507
508static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = {
509 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0),
510 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0),
511 ARM64_FTR_END,

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2292}
2293#endif /* CONFIG_ARM64_E0PD */
2294
2295#ifdef CONFIG_ARM64_PSEUDO_NMI
2296static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
2297 int scope)
2298{
2299 /*
2299 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU
2300 * ARM64_HAS_GIC_CPUIF_SYSREGS has a lower index, and is a boot CPU
2300 * feature, so will be detected earlier.
2301 */
2301 * feature, so will be detected earlier.
2302 */
2302 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF);
2303 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF))
2303 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GIC_CPUIF_SYSREGS);
2304 if (!cpus_have_cap(ARM64_HAS_GIC_CPUIF_SYSREGS))
2304 return false;
2305
2306 return enable_pseudo_nmi;
2307}
2308
2309static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2310 int scope)
2311{

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2491 .matches = has_always,
2492 },
2493 {
2494 .capability = ARM64_ALWAYS_SYSTEM,
2495 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2496 .matches = has_always,
2497 },
2498 {
2305 return false;
2306
2307 return enable_pseudo_nmi;
2308}
2309
2310static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry,
2311 int scope)
2312{

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2492 .matches = has_always,
2493 },
2494 {
2495 .capability = ARM64_ALWAYS_SYSTEM,
2496 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
2497 .matches = has_always,
2498 },
2499 {
2499 .desc = "GICv3 CPU interface",
2500 .capability = ARM64_HAS_GICV3_CPUIF,
2500 .desc = "GIC system register CPU interface",
2501 .capability = ARM64_HAS_GIC_CPUIF_SYSREGS,
2501 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2502 .matches = has_useable_gicv3_cpuif,
2503 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
2504 },
2505 {
2506 .desc = "Enhanced Counter Virtualization",
2507 .capability = ARM64_HAS_ECV,
2508 .type = ARM64_CPUCAP_SYSTEM_FEATURE,

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3057 {
3058 .desc = "PMUv3",
3059 .capability = ARM64_HAS_PMUV3,
3060 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3061 .matches = has_pmuv3,
3062 },
3063#endif
3064 {
2502 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
2503 .matches = has_useable_gicv3_cpuif,
2504 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP)
2505 },
2506 {
2507 .desc = "Enhanced Counter Virtualization",
2508 .capability = ARM64_HAS_ECV,
2509 .type = ARM64_CPUCAP_SYSTEM_FEATURE,

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3058 {
3059 .desc = "PMUv3",
3060 .capability = ARM64_HAS_PMUV3,
3061 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3062 .matches = has_pmuv3,
3063 },
3064#endif
3065 {
3065 .desc = "GICv5 CPU interface",
3066 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
3067 .capability = ARM64_HAS_GICV5_CPUIF,
3066 .desc = "SCTLR2",
3067 .capability = ARM64_HAS_SCTLR2,
3068 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
3068 .matches = has_cpuid_feature,
3069 .matches = has_cpuid_feature,
3069 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP)
3070 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP)
3070 },
3071 {},
3072};
3073
3074#define HWCAP_CPUID_MATCH(reg, field, min_value) \
3075 .matches = has_user_cpuid_feature, \
3076 ARM64_CPUID_FIELDS(reg, field, min_value)
3077

--- 944 unchanged lines hidden --- 		3071 },
3072 {},
3073};
3074
3075#define HWCAP_CPUID_MATCH(reg, field, min_value) \
3076 .matches = has_user_cpuid_feature, \
3077 ARM64_CPUID_FIELDS(reg, field, min_value)
3078

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