| sysreg.h (7d751b313dd9b4cb3a33812cf827decb48352d0b) | sysreg.h (cfa3a6c55b61a062afa1ccd8bca45fd270dd3d0f) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 --- 185 unchanged lines hidden (view full) --- 194#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 195 196#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 197#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 198 199#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 200#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 201 | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 --- 185 unchanged lines hidden (view full) --- 194#define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1) 195 196#define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0) 197#define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1) 198 199#define SYS_ID_AA64AFR0_EL1 sys_reg(3, 0, 0, 5, 4) 200#define SYS_ID_AA64AFR1_EL1 sys_reg(3, 0, 0, 5, 5) 201 |
| 202#define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2) 203 | |
| 204#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 205#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 206#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 207 208#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 209 210#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 211 --- 532 unchanged lines hidden (view full) --- 744#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 745 746#ifdef CONFIG_ARM64_PA_BITS_52 747#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 748#else 749#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 750#endif 751 | 202#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 203#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 204#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 205 206#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1) 207 208#define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2) 209 --- 532 unchanged lines hidden (view full) --- 742#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 743 744#ifdef CONFIG_ARM64_PA_BITS_52 745#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 746#else 747#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 748#endif 749 |
| 752/* id_aa64mmfr2 */ 753#define ID_AA64MMFR2_EL1_E0PD_SHIFT 60 754#define ID_AA64MMFR2_EL1_EVT_SHIFT 56 755#define ID_AA64MMFR2_EL1_BBM_SHIFT 52 756#define ID_AA64MMFR2_EL1_TTL_SHIFT 48 757#define ID_AA64MMFR2_EL1_FWB_SHIFT 40 758#define ID_AA64MMFR2_EL1_IDS_SHIFT 36 759#define ID_AA64MMFR2_EL1_AT_SHIFT 32 760#define ID_AA64MMFR2_EL1_ST_SHIFT 28 761#define ID_AA64MMFR2_EL1_NV_SHIFT 24 762#define ID_AA64MMFR2_EL1_CCIDX_SHIFT 20 763#define ID_AA64MMFR2_EL1_VARange_SHIFT 16 764#define ID_AA64MMFR2_EL1_IESB_SHIFT 12 765#define ID_AA64MMFR2_EL1_LSM_SHIFT 8 766#define ID_AA64MMFR2_EL1_UAO_SHIFT 4 767#define ID_AA64MMFR2_EL1_CnP_SHIFT 0 768 | |
| 769/* id_aa64dfr0 */ 770#define ID_AA64DFR0_MTPMU_SHIFT 48 771#define ID_AA64DFR0_TRBE_SHIFT 44 772#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 773#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 774#define ID_AA64DFR0_PMSVER_SHIFT 32 775#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 776#define ID_AA64DFR0_WRPS_SHIFT 20 --- 386 unchanged lines hidden --- | 750/* id_aa64dfr0 */ 751#define ID_AA64DFR0_MTPMU_SHIFT 48 752#define ID_AA64DFR0_TRBE_SHIFT 44 753#define ID_AA64DFR0_TRACE_FILT_SHIFT 40 754#define ID_AA64DFR0_DOUBLELOCK_SHIFT 36 755#define ID_AA64DFR0_PMSVER_SHIFT 32 756#define ID_AA64DFR0_CTX_CMPS_SHIFT 28 757#define ID_AA64DFR0_WRPS_SHIFT 20 --- 386 unchanged lines hidden --- |