sysreg.h (58e010516ee63b04863de7030858670d1fc93471) sysreg.h (d044a9fbace769c0f47b52ab8bc39f69e8a6e922)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Macros for accessing system registers with older binutils.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8

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160#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
161#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
162#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
163
164#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
165#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
166#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
167
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Macros for accessing system registers with older binutils.
4 *
5 * Copyright (C) 2014 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
7 */
8

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160#define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
161#define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
162#define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
163
164#define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
165#define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
166#define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
167
168#define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
169#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
170
171#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
172#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
173#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
174
175#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
176

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665#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
666
667#ifdef CONFIG_ARM64_PA_BITS_52
668#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52
669#else
670#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
671#endif
672
168#define SYS_ID_DFR1_EL1 sys_reg(3, 0, 0, 3, 5)
169
170#define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
171#define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
172#define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
173
174#define SYS_TRFCR_EL1 sys_reg(3, 0, 1, 2, 1)
175

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664#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
665
666#ifdef CONFIG_ARM64_PA_BITS_52
667#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52
668#else
669#define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48
670#endif
671
673#define ID_DFR0_EL1_PerfMon_PMUv3 0x3
674#define ID_DFR0_EL1_PerfMon_PMUv3p1 0x4
675#define ID_DFR0_EL1_PerfMon_PMUv3p4 0x5
676#define ID_DFR0_EL1_PerfMon_PMUv3p5 0x6
677
678#define ID_DFR1_EL1_MTPMU_SHIFT 0
679
672#define ID_DFR1_EL1_MTPMU_SHIFT 0
673
680#define ID_DFR0_EL1_PerfMon_SHIFT 24
681#define ID_DFR0_EL1_MProfDbg_SHIFT 20
682#define ID_DFR0_EL1_MMapTrc_SHIFT 16
683#define ID_DFR0_EL1_CopTrc_SHIFT 12
684#define ID_DFR0_EL1_MMapDbg_SHIFT 8
685#define ID_DFR0_EL1_CopSDbg_SHIFT 4
686#define ID_DFR0_EL1_CopDbg_SHIFT 0
687
688#if defined(CONFIG_ARM64_4K_PAGES)
689#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
690#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
691#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
692#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
693#elif defined(CONFIG_ARM64_16K_PAGES)
694#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
695#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN

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674#if defined(CONFIG_ARM64_4K_PAGES)
675#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT
676#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
677#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
678#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
679#elif defined(CONFIG_ARM64_16K_PAGES)
680#define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT
681#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN

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