| pgtable-hwdef.h (79790b6818e96c58fe2bffee1b418c16e64e7b80) | pgtable-hwdef.h (6ccc971ee2c61a1ffb487e46bf6184f7df6aacfb) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5#ifndef __ASM_PGTABLE_HWDEF_H 6#define __ASM_PGTABLE_HWDEF_H 7 8#include <asm/memory.h> --- 283 unchanged lines hidden (view full) --- 292#define TCR_IPS_SHIFT 32 293#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) 294#define TCR_A1 (UL(1) << 22) 295#define TCR_ASID16 (UL(1) << 36) 296#define TCR_TBI0 (UL(1) << 37) 297#define TCR_TBI1 (UL(1) << 38) 298#define TCR_HA (UL(1) << 39) 299#define TCR_HD (UL(1) << 40) | 1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5#ifndef __ASM_PGTABLE_HWDEF_H 6#define __ASM_PGTABLE_HWDEF_H 7 8#include <asm/memory.h> --- 283 unchanged lines hidden (view full) --- 292#define TCR_IPS_SHIFT 32 293#define TCR_IPS_MASK (UL(7) << TCR_IPS_SHIFT) 294#define TCR_A1 (UL(1) << 22) 295#define TCR_ASID16 (UL(1) << 36) 296#define TCR_TBI0 (UL(1) << 37) 297#define TCR_TBI1 (UL(1) << 38) 298#define TCR_HA (UL(1) << 39) 299#define TCR_HD (UL(1) << 40) |
| 300#define TCR_TBID0 (UL(1) << 51) |
|
| 300#define TCR_TBID1 (UL(1) << 52) 301#define TCR_NFD0 (UL(1) << 53) 302#define TCR_NFD1 (UL(1) << 54) 303#define TCR_E0PD0 (UL(1) << 55) 304#define TCR_E0PD1 (UL(1) << 56) 305#define TCR_TCMA0 (UL(1) << 57) 306#define TCR_TCMA1 (UL(1) << 58) 307#define TCR_DS (UL(1) << 59) --- 18 unchanged lines hidden --- | 301#define TCR_TBID1 (UL(1) << 52) 302#define TCR_NFD0 (UL(1) << 53) 303#define TCR_NFD1 (UL(1) << 54) 304#define TCR_E0PD0 (UL(1) << 55) 305#define TCR_E0PD1 (UL(1) << 56) 306#define TCR_TCMA0 (UL(1) << 57) 307#define TCR_TCMA1 (UL(1) << 58) 308#define TCR_DS (UL(1) << 59) --- 18 unchanged lines hidden --- |