r9a07g054.dtsi (c2b0dc0e83ef4a74cbe381fd0c84cea16cf067f0) r9a07g054.dtsi (05d11e2f4460752fa5f7ce7657e1b040056c1736)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 732 unchanged lines hidden (view full) ---

741 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
742 interrupt-names = "error",
743 "ch0", "ch1", "ch2", "ch3",
744 "ch4", "ch5", "ch6", "ch7",
745 "ch8", "ch9", "ch10", "ch11",
746 "ch12", "ch13", "ch14", "ch15";
747 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
748 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 732 unchanged lines hidden (view full) ---

741 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
742 interrupt-names = "error",
743 "ch0", "ch1", "ch2", "ch3",
744 "ch4", "ch5", "ch6", "ch7",
745 "ch8", "ch9", "ch10", "ch11",
746 "ch12", "ch13", "ch14", "ch15";
747 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
748 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
749 clock-names = "main", "register";
749 power-domains = <&cpg>;
750 resets = <&cpg R9A07G054_DMAC_ARESETN>,
751 <&cpg R9A07G054_DMAC_RST_ASYNC>;
750 power-domains = <&cpg>;
751 resets = <&cpg R9A07G054_DMAC_ARESETN>,
752 <&cpg R9A07G054_DMAC_RST_ASYNC>;
753 reset-names = "arst", "rst_async";
752 #dma-cells = <1>;
753 dma-channels = <16>;
754 };
755
756 gpu: gpu@11840000 {
757 compatible = "renesas,r9a07g054-mali",
758 "arm,mali-bifrost";
759 reg = <0x0 0x11840000 0x0 0x10000>;

--- 316 unchanged lines hidden --- 		754 #dma-cells = <1>;
755 dma-channels = <16>;
756 };
757
758 gpu: gpu@11840000 {
759 compatible = "renesas,r9a07g054-mali",
760 "arm,mali-bifrost";
761 reg = <0x0 0x11840000 0x0 0x10000>;

--- 316 unchanged lines hidden ---