r9a07g054.dtsi (594ce0b8a998aa4d05827cd7c0d0dcec9a1e3ae2) r9a07g054.dtsi (046084b5e1426efbf08913830bdb101dcbb06be5)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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1053 interrupt-controller;
1054 reg = <0x0 0x11900000 0 0x40000>,
1055 <0x0 0x11940000 0 0x60000>;
1056 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1057 };
1058
1059 sdhi0: mmc@11c00000 {
1060 compatible = "renesas,sdhi-r9a07g054",
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/V2L SoC
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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1053 interrupt-controller;
1054 reg = <0x0 0x11900000 0 0x40000>,
1055 <0x0 0x11940000 0 0x60000>;
1056 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1057 };
1058
1059 sdhi0: mmc@11c00000 {
1060 compatible = "renesas,sdhi-r9a07g054",
1061 "renesas,rcar-gen3-sdhi";
1061 "renesas,rzg2l-sdhi";
1062 reg = <0x0 0x11c00000 0 0x10000>;
1063 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1066 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1067 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1068 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1069 clock-names = "core", "clkh", "cd", "aclk";
1070 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1071 power-domains = <&cpg>;
1072 status = "disabled";
1073 };
1074
1075 sdhi1: mmc@11c10000 {
1076 compatible = "renesas,sdhi-r9a07g054",
1062 reg = <0x0 0x11c00000 0 0x10000>;
1063 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1066 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1067 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1068 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1069 clock-names = "core", "clkh", "cd", "aclk";
1070 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1071 power-domains = <&cpg>;
1072 status = "disabled";
1073 };
1074
1075 sdhi1: mmc@11c10000 {
1076 compatible = "renesas,sdhi-r9a07g054",
1077 "renesas,rcar-gen3-sdhi";
1077 "renesas,rzg2l-sdhi";
1078 reg = <0x0 0x11c10000 0 0x10000>;
1079 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1082 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1083 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1084 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1085 clock-names = "core", "clkh", "cd", "aclk";

--- 262 unchanged lines hidden --- 		1078 reg = <0x0 0x11c10000 0 0x10000>;
1079 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1082 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1083 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1084 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1085 clock-names = "core", "clkh", "cd", "aclk";

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