r9a07g044.dtsi (5da750ddd96454757a3b467e968e3fb70bb12bc8) r9a07g044.dtsi (05d11e2f4460752fa5f7ce7657e1b040056c1736)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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735 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
736 interrupt-names = "error",
737 "ch0", "ch1", "ch2", "ch3",
738 "ch4", "ch5", "ch6", "ch7",
739 "ch8", "ch9", "ch10", "ch11",
740 "ch12", "ch13", "ch14", "ch15";
741 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
742 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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735 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
736 interrupt-names = "error",
737 "ch0", "ch1", "ch2", "ch3",
738 "ch4", "ch5", "ch6", "ch7",
739 "ch8", "ch9", "ch10", "ch11",
740 "ch12", "ch13", "ch14", "ch15";
741 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
742 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
743 clock-names = "main", "register";
743 power-domains = <&cpg>;
744 resets = <&cpg R9A07G044_DMAC_ARESETN>,
745 <&cpg R9A07G044_DMAC_RST_ASYNC>;
744 power-domains = <&cpg>;
745 resets = <&cpg R9A07G044_DMAC_ARESETN>,
746 <&cpg R9A07G044_DMAC_RST_ASYNC>;
747 reset-names = "arst", "rst_async";
746 #dma-cells = <1>;
747 dma-channels = <16>;
748 };
749
750 gpu: gpu@11840000 {
751 compatible = "renesas,r9a07g044-mali",
752 "arm,mali-bifrost";
753 reg = <0x0 0x11840000 0x0 0x10000>;

--- 316 unchanged lines hidden --- 		748 #dma-cells = <1>;
749 dma-channels = <16>;
750 };
751
752 gpu: gpu@11840000 {
753 compatible = "renesas,r9a07g044-mali",
754 "arm,mali-bifrost";
755 reg = <0x0 0x11840000 0x0 0x10000>;

--- 316 unchanged lines hidden ---