r9a07g044.dtsi (594ce0b8a998aa4d05827cd7c0d0dcec9a1e3ae2) r9a07g044.dtsi (046084b5e1426efbf08913830bdb101dcbb06be5)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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1045 interrupt-controller;
1046 reg = <0x0 0x11900000 0 0x40000>,
1047 <0x0 0x11940000 0 0x60000>;
1048 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 };
1050
1051 sdhi0: mmc@11c00000 {
1052 compatible = "renesas,sdhi-r9a07g044",
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 1036 unchanged lines hidden (view full) ---

1045 interrupt-controller;
1046 reg = <0x0 0x11900000 0 0x40000>,
1047 <0x0 0x11940000 0 0x60000>;
1048 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 };
1050
1051 sdhi0: mmc@11c00000 {
1052 compatible = "renesas,sdhi-r9a07g044",
1053 "renesas,rcar-gen3-sdhi";
1053 "renesas,rzg2l-sdhi";
1054 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", "clkh", "cd", "aclk";
1062 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg>;
1064 status = "disabled";
1065 };
1066
1067 sdhi1: mmc@11c10000 {
1068 compatible = "renesas,sdhi-r9a07g044",
1054 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", "clkh", "cd", "aclk";
1062 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg>;
1064 status = "disabled";
1065 };
1066
1067 sdhi1: mmc@11c10000 {
1068 compatible = "renesas,sdhi-r9a07g044",
1069 "renesas,rcar-gen3-sdhi";
1069 "renesas,rzg2l-sdhi";
1070 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", "clkh", "cd", "aclk";

--- 262 unchanged lines hidden --- 		1070 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", "clkh", "cd", "aclk";

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