r9a07g043u.dtsi (49669da644cf000eb79dbede55bd04acf3f2f0a0) r9a07g043u.dtsi (b9a0be2054964026aa58966ce9724b672f210835)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
11
12#include "r9a07g043.dtsi"
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9
10#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
11
12#include "r9a07g043.dtsi"
13
14/ {
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 compatible = "arm,cortex-a55";
21 reg = <0>;
22 device_type = "cpu";
23 #cooling-cells = <2>;
24 next-level-cache = <&L3_CA55>;
25 enable-method = "psci";
26 clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
27 operating-points-v2 = <&cluster0_opp>;
28 };
29
30 L3_CA55: cache-controller-0 {
31 compatible = "cache";
32 cache-unified;
33 cache-size = <0x40000>;
34 };
35 };
36
37 psci {
38 compatible = "arm,psci-1.0", "arm,psci-0.2";
39 method = "smc";
40 };
41
42 timer {
43 compatible = "arm,armv8-timer";
44 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
45 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
46 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
47 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
48 };
49};
50
51&soc {
52 interrupt-parent = <&gic>;
53
54 gic: interrupt-controller@11900000 {
55 compatible = "arm,gic-v3";
56 #interrupt-cells = <3>;
57 #address-cells = <0>;
58 interrupt-controller;
59 reg = <0x0 0x11900000 0 0x40000>,
60 <0x0 0x11940000 0 0x60000>;
61 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
62 };
63};
64
65&sysc {
66 interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
67 <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
68 <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
69 <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-names = "lpm_int", "ca55stbydone_int",
71 "cm33stbyr_int", "ca55_deny";
72};