r9a07g043.dtsi (f52e14095e56ab6470d959f08e40aa2e45cb85cd) r9a07g043.dtsi (1de1b44833e394e63119fcff37e458a94c244799)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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286 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
287 clock-names = "fck";
288 power-domains = <&cpg>;
289 resets = <&cpg R9A07G043_SCI1_RST>;
290 status = "disabled";
291 };
292
293 canfd: can@10050000 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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286 clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
287 clock-names = "fck";
288 power-domains = <&cpg>;
289 resets = <&cpg R9A07G043_SCI1_RST>;
290 status = "disabled";
291 };
292
293 canfd: can@10050000 {
294 compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
294 reg = <0 0x10050000 0 0x8000>;
295 reg = <0 0x10050000 0 0x8000>;
295 /* place holder */
296 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
304 interrupt-names = "g_err", "g_recc",
305 "ch0_err", "ch0_rec", "ch0_trx",
306 "ch1_err", "ch1_rec", "ch1_trx";
307 clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
308 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
309 <&can_clk>;
310 clock-names = "fck", "canfd", "can_clk";
311 assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
312 assigned-clock-rates = <50000000>;
313 resets = <&cpg R9A07G043_CANFD_RSTP_N>,
314 <&cpg R9A07G043_CANFD_RSTC_N>;
315 reset-names = "rstp_n", "rstc_n";
316 power-domains = <&cpg>;
317 status = "disabled";
318
319 channel0 {
320 status = "disabled";
321 };
322 channel1 {
323 status = "disabled";
324 };
296 };
297
298 i2c0: i2c@10058000 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
302 reg = <0 0x10058000 0 0x400>;
303 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,

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326
327 i2c0: i2c@10058000 {
328 #address-cells = <1>;
329 #size-cells = <0>;
330 compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
331 reg = <0 0x10058000 0 0x400>;
332 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,

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