r9a07g043.dtsi (e42faad1ef822e186c20e60576b198e1ac9866c4) r9a07g043.dtsi (a8352a5158ed032fa6c0d433fefc63285fdac8b0)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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689 renesas,buswait = <7>;
690 phys = <&usb2_phy0 3>;
691 phy-names = "usb";
692 power-domains = <&cpg>;
693 status = "disabled";
694 };
695
696 wdt0: watchdog@12800800 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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689 renesas,buswait = <7>;
690 phys = <&usb2_phy0 3>;
691 phy-names = "usb";
692 power-domains = <&cpg>;
693 status = "disabled";
694 };
695
696 wdt0: watchdog@12800800 {
697 compatible = "renesas,r9a07g043-wdt",
698 "renesas,rzg2l-wdt";
697 reg = <0 0x12800800 0 0x400>;
699 reg = <0 0x12800800 0 0x400>;
698 /* place holder */
700 clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
701 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
702 clock-names = "pclk", "oscclk";
703 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
705 interrupt-names = "wdt", "perrout";
706 resets = <&cpg R9A07G043_WDT0_PRESETN>;
707 power-domains = <&cpg>;
708 status = "disabled";
699 };
700
701 wdt2: watchdog@12800400 {
709 };
710
711 wdt2: watchdog@12800400 {
712 compatible = "renesas,r9a07g043-wdt",
713 "renesas,rzg2l-wdt";
702 reg = <0 0x12800400 0 0x400>;
714 reg = <0 0x12800400 0 0x400>;
703 /* place holder */
715 clocks = <&cpg CPG_MOD R9A07G043_WDT2_PCLK>,
716 <&cpg CPG_MOD R9A07G043_WDT2_CLK>;
717 clock-names = "pclk", "oscclk";
718 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
720 interrupt-names = "wdt", "perrout";
721 resets = <&cpg R9A07G043_WDT2_PRESETN>;
722 power-domains = <&cpg>;
723 status = "disabled";
704 };
705
706 ostm0: timer@12801000 {
707 compatible = "renesas,r9a07g043-ostm",
708 "renesas,ostm";
709 reg = <0x0 0x12801000 0x0 0x400>;
710 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
711 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;

--- 36 unchanged lines hidden --- 		724 };
725
726 ostm0: timer@12801000 {
727 compatible = "renesas,r9a07g043-ostm",
728 "renesas,ostm";
729 reg = <0x0 0x12801000 0x0 0x400>;
730 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
731 clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;

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