r9a07g043.dtsi (cf40c9689e5109bf5e4c29038c9f450223aaad2b) r9a07g043.dtsi (2d10555298576a95b637a5087751d0aad570964d)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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270 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "lpm_int", "ca55stbydone_int",
273 "cm33stbyr_int", "ca55_deny";
274 status = "disabled";
275 };
276
277 pinctrl: pinctrl@11030000 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

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270 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "lpm_int", "ca55stbydone_int",
273 "cm33stbyr_int", "ca55_deny";
274 status = "disabled";
275 };
276
277 pinctrl: pinctrl@11030000 {
278 compatible = "renesas,r9a07g043-pinctrl";
278 reg = <0 0x11030000 0 0x10000>;
279 gpio-controller;
280 #gpio-cells = <2>;
279 reg = <0 0x11030000 0 0x10000>;
280 gpio-controller;
281 #gpio-cells = <2>;
281 /* place holder */
282 gpio-ranges = <&pinctrl 0 0 152>;
283 clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
284 power-domains = <&cpg>;
285 resets = <&cpg R9A07G043_GPIO_RSTN>,
286 <&cpg R9A07G043_GPIO_PORT_RESETN>,
287 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
282 };
283
284 dmac: dma-controller@11820000 {
285 compatible = "renesas,r9a07g043-dmac",
286 "renesas,rz-dmac";
287 reg = <0 0x11820000 0 0x10000>,
288 <0 0x11830000 0 0x10000>;
289 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,

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288 };
289
290 dmac: dma-controller@11820000 {
291 compatible = "renesas,r9a07g043-dmac",
292 "renesas,rz-dmac";
293 reg = <0 0x11820000 0 0x10000>,
294 <0 0x11830000 0 0x10000>;
295 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,

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