r9a07g043.dtsi (c2ff5c0282f94c1f1f81007e1fa7378fe95f46d3) r9a07g043.dtsi (470218e29daf7f1de9f4d1af16c7ecf54344f6a1)
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 484 unchanged lines hidden (view full) ---

493 reg = <0 0x10059400 0 0x400>;
494 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
495 resets = <&cpg R9A07G043_TSU_PRESETN>;
496 power-domains = <&cpg>;
497 #thermal-sensor-cells = <1>;
498 };
499
500 sbc: spi@10060000 {
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SoC
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/interrupt-controller/arm-gic.h>

--- 484 unchanged lines hidden (view full) ---

493 reg = <0 0x10059400 0 0x400>;
494 clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
495 resets = <&cpg R9A07G043_TSU_PRESETN>;
496 power-domains = <&cpg>;
497 #thermal-sensor-cells = <1>;
498 };
499
500 sbc: spi@10060000 {
501 compatible = "renesas,r9a07g043-rpc-if",
502 "renesas,rzg2l-rpc-if";
501 reg = <0 0x10060000 0 0x10000>,
502 <0 0x20000000 0 0x10000000>,
503 <0 0x10070000 0 0x10000>;
503 reg = <0 0x10060000 0 0x10000>,
504 <0 0x20000000 0 0x10000000>,
505 <0 0x10070000 0 0x10000>;
506 reg-names = "regs", "dirmap", "wbuf";
507 clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
508 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
509 resets = <&cpg R9A07G043_SPI_RST>;
510 power-domains = <&cpg>;
504 #address-cells = <1>;
505 #size-cells = <0>;
511 #address-cells = <1>;
512 #size-cells = <0>;
506 /* place holder */
513 status = "disabled";
507 };
508
509 cpg: clock-controller@11010000 {
510 compatible = "renesas,r9a07g043-cpg";
511 reg = <0 0x11010000 0 0x10000>;
512 clocks = <&extal_clk>;
513 clock-names = "extal";
514 #clock-cells = <2>;

--- 364 unchanged lines hidden --- 		514 };
515
516 cpg: clock-controller@11010000 {
517 compatible = "renesas,r9a07g043-cpg";
518 reg = <0 0x11010000 0 0x10000>;
519 clocks = <&extal_clk>;
520 clock-names = "extal";
521 #clock-cells = <2>;

--- 364 unchanged lines hidden ---